Board feature control

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Revision as of 01:53, 21 December 2018 by wiki>Ped7g (Extending limit of queried Next Control Registers to 100, as there's now 50+ of them.)
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This is a general list of ports and registers used to control features on the Spectrum Next board.

Note that these lists are automatically generated and not directly editable. To edit data on a port or register, visit its page. To add a new port, click here. To add a new register, click here.

Mapped Spectrum Ports

A note on partial decoding

Most Spectrum peripherals did not actually decode all 16 bits of the address bus; they checked only for certain bits, and would respond if those bit values were set correctly, regardless of the other bits. The "bitmask" column for each port shows the bits that are tested for by the device. Traditionally all "unused" bits are set to 1 to avoid conflicts with other devices, which is the basis of the given port numbers; but alternate port numbers may be used in some cases. However, beware of creating clashes: in particular any port which does not intend to access the ULA should have the LSB set, as the ULA checks only for a reset LSB.

It is not known if the Next's built-in devices will have this decoding restriction, but it seems a safe presumption that they will not except where needed by legacy code.

On the other hand, partial decoding can allow use of the multiple output opcodes such as OTIR, which normally places the loop counter on the top half of the address bus - thus making it useless except for devices which ignore this top half. This is the reason why some of the Next registers do ignore the top half of the port address.

 NumberMaskDescription
Keyboard$**FE%xxxx xxxx ---- ---0 where only one bit in x is 0Series of specific ports that read keyboard key presses.
I2C clock$103B%0001 0000 0011 1011 ??Sets and reads the I2C SCL line.
I2C data$113B%0001 0001 0011 1011 ??Sets and reads the I2C SDA line
Layer 2 Access Port$123B%0001 0010 0011 1011 ??Enables Layer 2 and controls paging of layer 2 screen into lower memory.
UART TX$133B%0001 0011 0011 1011Sends byte to serial port. If read, tells if data in RX buffer
UART RX$143B%0001 0100 0011 1011Reads data from serial port, write sets the baudrate
UART Control$153B%0001 0101 0011 1011Configuration of UART interfaces
UART Frame$163B%0001 0110 0011 1011UART Frame
CTC Channels$183B%0001 1XXX 0011 1011CTC 8 channels 0x183b - 0x1f3b
Plus 3 Memory Paging Control$1FFD%0001 ---- ---- --0-Controls ROM paging and special paging options from the +2a/+3.
TBBlue Register Select$243B%0010 0100 0011 1011Selects active port for TBBlue/Next feature configuration.
TBBlue Register Access$253B%0010 0101 0011 1011Reads and/or writes the selected TBBlue control register.
Sprite Status/Slot Select$303B%0011 0000 0011 1011 ??Sets active sprite-attribute index and pattern-slot index, reads sprite status.
Memory Paging Control$7FFD%01-- ---- ---- --0-Selects active RAM, ROM, and displayed screen.
Sound Chip Register Write$BFFD%10-- ---- ---- --0-Writes to the selected register of the selected sound chip.
Next Memory Bank Select$DFFD%1101 1111 1111 1101Provides additional bank select bits for extended memory.
DIVMMC$E3Divmmc control
Kempston Mouse Buttons$FADF%---- ---0 --0- ----Reads buttons on Kempston Mouse.
Kempston Mouse X$FBDF%---- -0-1 --0- ----X coordinate of Kempston Mouse, 0-255.
Kempston Mouse Y$FFDF%---- -1-1 --0- ----Y coordinate of Kempston Mouse, 0-192.
Turbo Sound Next Control$FFFD%11-- ---- ---- --0-Controls stereo channels and selects active sound chip and sound chip channel.
MB02 DMA Port$xx0B---- ---- 0000 1011Controls Z8410 DMA chip via MB02 standard.
Kempston Joystick$xx1F%---- ---- 0001 1111Reads movement of joysticks using Kempston interface.
Kempston Joystick 2, Joystick I/O$xx37Kempston interface second joystick variant and controls joystick I/O.
Sprite Attribute Upload$xx57%---- ---- 0101 0111Uploads sprite positions, visibility, colour type and effect flags.
Sprite Pattern Upload$xx5B%---- ---- 0101 1011 ??Used to upload the pattern of the selected sprite.
Datagear DMA Port$xx6B---- ---- 0110 1011Controls zxnDMA chip
SpecDrum DAC Output$xxDF%---- ---- --01 1111Output to SpecDrum DAC.
ULA Control Port$xxFEControls border color and base Spectrum audio settings.
Timex Sinclair Video Mode Control$xxFFControls Timex Sinclair video modes and colours in hi-res mode.

Next/TBBlue Feature Control Registers

Specific features of the Next are controlled via these register numbers, accessed via TBBlue Register Select ($243B / 9275) and TBBlue Register Access ($253B / 9531), or via the NEXTREG opcode.

 NumberReadableWritableDescription
Machine ID Register$00truefalseIdentifies TBBlue board type. Should always be 10 on Next.
Core Version Register$01truefalseIdentifies core (FPGA image) version.
Next Reset Register$02truetrueIdentifies type of last reset. Can be written to force reset.
Machine Type Register$03truetrueIdentifies timing and machine type.
Config Mapping Register$04falsetrueIn config mode, allows RAM to be mapped to ROM area.
Peripheral 1 Register$05truetrueSets joystick mode, video frequency and Scandoubler.
Peripheral 2 Register$06truetrueEnables CPU Speed key, DivMMC, Multiface, Mouse and AY audio.
CPU Speed Register$07truetrueSets CPU Speed, reads actual speed.
Peripheral 3 Register$08truetrueABC/ACB Stereo, Internal Speaker, SpecDrum, Timex Video Modes, Turbo Sound Next, RAM contention and [un]lock 128k paging.
Peripheral 4 Register$09truetrueSets scanlines, AY mono output, Sprite-id lockstep, reset DivMMC mapram and disable HDMI audio.
Peripheral 5 Register$0AtruetrueMouse buttons and DPI config
Core Version Register (sub minor)$0EtruefalseIdentifies core (FPGA image) version (sub minor number).
Anti-brick Register$10truetrueUsed within the Anti-brick system.
Video Timing Register$11truetrueSets video output timing variant.
Layer 2 RAM Page Register$12truetrueSets the bank number where Layer 2 video memory begins.
Layer 2 RAM Shadow Page Register$13truetrueSets the bank number where the Layer 2 shadow screen begins.
Global Transparency Register$14truetrueSets the "transparent" colour for Layer 2, ULA and LoRes pixel data.
Sprite and Layers System Register$15truetrueEnables/disables Sprites and Lores Layer, and chooses priority of sprites and Layer 2.
Layer 2 X Offset Register$16truetrueSets the pixel offset used for drawing Layer 2 graphics on the screen.
Layer 2 Y Offset Register$17truetrueSets the Y offset used when drawing Layer 2 graphics on the screen.
Clip Window Layer 2 Register$18truetrueSets and reads clip-window for Layer 2.
Clip Window Sprites Register$19truetrueSets and reads clip-window for Sprites
Clip Window ULA/LoRes Register$1AtruetrueSets and reads clip-window for ULA/LoRes layer.
Clip Window Tilemap Register$1BtruetrueSets and reads clip-window for Tilemap.
Clip Window Control Register$1CtruetrueControls (resets) the clip-window registers indices.
Active Video Line MSB Register$1EtruefalseHolds the MSB (only, as bit 0) of the raster line currently being drawn.
Active Video Line LSB Register$1FtruefalseHolds the eight LSBs of the raster line currently being drawn.
Video Line Interrupt Control Register$22truetrueControls the timing of raster interrupts and the ULA frame interrupt.
Video Line Interrupt Value Register$23truetrueHolds the eight LSBs of the line on which a raster interrupt should occur.
ULA X Offset Register$26truetruePixel X offset (0..255) to use when drawing ULA Layer.
ULA Y Offset Register$27truetruePixel Y offset (0..191) to use when drawing ULA Layer.
Keymap High Address Register$28truetruePS/2 Keymap address MSB, read (pending) first byte of palette colour
Keymap Low Address Register$29falsetruePS/2 Keymap address LSB.
Keymap High Data Register$2AfalsetrueHigh data to PS/2 Keymap (MSB of data in bit 0)
Keymap Low Data Register$2BfalsetrueLow eight LSBs of PS/2 Keymap data.
DAC B (left) mirror Register$2CtruetrueDAC B mirror, read current I2S left MSB
DAC A+D (mono) mirror Register$2DtruetrueSpecDrum port 0xDF / DAC A+D mirror, read current I2S LSB
DAC C (right) mirror Register$2EtruetrueDAC C mirror, read current I2S right MSB
Tilemap Offset X MSB Register$2FtruetrueSets the pixel offset (two high bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset X LSB Register$30truetrueSets the pixel offset (eight low bits) used for drawing Tilemap graphics on the screen.
Tilemap Offset Y Register$31truetrueSets the pixel offset used for drawing Tilemap graphics on the screen.
LoRes X Offset Register$32truetruePixel X offset (0..255) to use when drawing LoRes Layer.
LoRes Y Offset Register$33truetruePixel Y offset (0..191) to use when drawing LoRes Layer.
Sprite port-mirror Index Register$34truetrueSelects sprite index 0..127 to be affected by writes to other Sprite ports (and mirrors).
Sprite port-mirror Attribute 0 Register$35falsetrueNextreg port-mirror to write directly into "byte 1" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 1 Register$36falsetrueNextreg port-mirror to write directly into "byte 2" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 2 Register$37falsetrueNextreg port-mirror to write directly into "byte 3" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 3 Register$38falsetrueNextreg port-mirror to write directly into "byte 4" of Sprite Attribute Upload ($xx57 / 87).
Sprite port-mirror Attribute 4 Register$39falsetrueNextreg port-mirror to write directly into "byte 5" of Sprite Attribute Upload ($xx57 / 87).
Palette Index Register$40truetrueChooses an palette element (index) to manipulate with
Palette Value Register$41truetrueUse to set/read 8-bit colours of the ULANext palette.
Enhanced ULA Ink Color Mask$42truetrueSpecifies mask to extract ink colour from attribute cell value in ULANext mode.
Enhanced ULA Control Register$43truetrueEnables or disables Enhanced ULA interpretation of attribute values and toggles active palette.
Enhanced ULA Palette Extension$44truetrueUse to set 9-bit (2-byte) colours of the Enhanced ULA palette, or to read second byte of colour.
Transparency colour fallback Register$4Atruetrue8-bit colour to be used when all layers contain transparent pixel.
Sprites Transparency Index Register$4BtruetrueIndex into sprite palette (of "transparent" colour).
Tilemap Transparency Index Register$4CtruetrueIndex into Tilemap palette (of "transparent" colour).
Memory management slot 0 bank$50truetrueSelects the 8k-bank stored in 8k-slot 0 (see Memory map).
Memory management slot 1 bank$51truetrueSelects the 8k-bank stored in 8k-slot 1 (see Memory map).
Memory management slot 2 bank$52truetrueSelects the 8k-bank stored in 8k-slot 2 (see Memory map).
Memory management slot 3 bank$53truetrueSelects the 8k-bank stored in 8k-slot 3 (see Memory map).
Memory management slot 4 bank$54truetrueSelects the 8k-bank stored in 8k-slot 4 (see Memory map).
Memory management slot 5 bank$55truetrueSelects the 8k-bank stored in 8k-slot 5 (see Memory map).
Memory management slot 6 bank$56truetrueSelects the 8k-bank stored in 8k-slot 6 (see Memory map).
Memory management slot 7 bank$57truetrueSelects the 8k-bank stored in 8k-slot 7 (see Memory map).
Copper Data$60falsetrueUsed to upload code to the Copper.
Copper Control Low Byte$61truetrueHolds low byte of Copper control bits.
Copper Control High Byte$62truetrueHolds high byte of Copper control flags.
Copper Data 16-bit Write Register$63falsetrueUsed to upload code to the Copper.
Vertical Video Line Offset Register$64truetrueOffset numbering of raster lines in copper/interrupt/active register
ULA Control Register$68truetrueDisable ULA, controls ULA mixing/blending, enable ULA+
Display Control 1 Register$69truetrueLayer2, ULA shadow, Timex $FF port
LoRes Control Register$6AtruetrueLoRes Radastan mode
Tilemap Control Register$6BtruetrueControls Tilemap mode.
Default Tilemap Attribute Register$6CtruetrueDefault tile attribute for 8-bit only maps.
Tilemap Base Address Register$6EtruetrueBase address of the 40x32 or 80x32 tile map (similar to text-mode of other computers).
Tile Definitions Base Address Register$6FtruetrueBase address of the tiles' graphics.
Layer 2 Control Register$70truetrueLayer 2 resolution, palette offset
Layer 2 X Offset MSB Register$71truetrueSets the pixel offset used for drawing Layer 2 graphics on the screen.
Sprite port-mirror Attribute 0 (with INC) Register$75falsetrueSame as Sprite port-mirror Attribute 0 Register ($35) (write first byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 1 (with INC) Register$76falsetrueSame as Sprite port-mirror Attribute 1 Register ($36) (write second byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 2 (with INC) Register$77falsetrueSame as Sprite port-mirror Attribute 2 Register ($37) (write third byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 3 (with INC) Register$78falsetrueSame as Sprite port-mirror Attribute 3 Register ($38) (write fourth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
Sprite port-mirror Attribute 4 (with INC) Register$79falsetrueThe same as Sprite port-mirror Attribute 4 Register ($39) (write fifth byte of sprite-attributes), plus increments Sprite port-mirror Index Register ($34)
User Storage 0 Register$7Ftruetrue8-bit storage for user
Expansion Bus Enable Register$80truetrueExpansion bus enable/config
Expansion Bus Control Register$81truetrueExpansion bus controls
Internal Port Decoding b0-7 Register$82truetrueEnabling internal ports decoding
Internal Port Decoding b8-15 Register$83truetrueEnabling internal ports decoding
Internal Port Decoding b16-23 Register$84truetrueEnabling internal ports decoding
Internal Port Decoding b24-31 Register$85truetrueEnabling internal ports decoding
Expansion Bus Decoding b0-7 Register$86truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b8-15 Register$87truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b16-23 Register$88truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus Decoding b24-31 Register$89truetrueWhen expansion bus is enabled: Internal ports decoding mask
Expansion Bus I/O Propagate Register$8AtruetrueMonitoring internal I/O or adding external keyboard
Alternate ROM$8CtruetrueEnable alternate ROM or lock 48k ROM
Memory Mapping Register$8EtruetrueControl classic Spectrum memory mapping
Pi GPIO Output Enable Register$90-$93truetrueEnables GPIO pins output
Pi GPIO Register$98-$9BtruetrueGPIO pins mapped to Next Register
... further results