Difference between revisions of "Anti-brick Register"

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(core 3.0 changes/refresh)
(trying to "fix" the description to be more in sync with official manual and latest nextreg.txt (still feels incomplete))
 
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'''Write''' bit mapped (only in config mode):
+
'''Write''' bit mapped:
 
{| class="wikitable"
 
{| class="wikitable"
 
! Bit !! Effect
 
! Bit !! Effect
 
|-
 
|-
| 7 || If 1 start selected core, if 0 FPGA loads the fixed anti-brick core
+
| 7 || Start selected core (reboot FPGA)
 
|-
 
|-
 
| 6-5 || Reserved, must be 0
 
| 6-5 || Reserved, must be 0
 
|-
 
|-
| 4-0 || Core ID 0-31 (default is 2)  
+
| 4-0 || Core ID 0-31 (default is 2) (only in config mode)
 
|}
 
|}
  
 
Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.
 
Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.

Latest revision as of 05:26, 6 April 2020

Number $10
Readable Yes
Writable Yes
Short Description Used within the Anti-brick system.

Read bit mapped:

Bit Effect
7-2 Reserved
1 Button DRIVE (DivMMC) is pressed
0 Button M1 (Multiface) is pressed

Write bit mapped:

Bit Effect
7 Start selected core (reboot FPGA)
6-5 Reserved, must be 0
4-0 Core ID 0-31 (default is 2) (only in config mode)

Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.