DIVMMC: Difference between revisions
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Created page with "{{Port |Number=$E3 |NumberDec=227 |ShortDesc=Divmmc control |Readable=Yes |Writable=Yes |Subsystem=DIVMMC }} 0xE3 Divmmc control (R/W) :bit 7 = conmem = 1 to map in divmmc..." |
fixing some formatting |
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* divmmc automatically maps itself in when instruction fetches hit specific addresses in the rom. When this happens, the esxdos rom (or divmmc bank 3 if mapram is set) appears in 0K-8K and the selected divmmc bank appears as ram in 8K-16K. | * divmmc automatically maps itself in when instruction fetches hit specific addresses in the rom. When this happens, the esxdos rom (or divmmc bank 3 if mapram is set) appears in 0K-8K and the selected divmmc bank appears as ram in 8K-16K. | ||
* bit 6 can only be set, once set only a power cycle can reset it on the original divmmc. | * bit 6 can only be set, once set only a power cycle can reset it on the original divmmc. nextreg 0x09 bit 3 can be set to reset this bit. | ||
The divmmc has been enhanced in the zx next to add more entry points and make them programmable. | The divmmc has been enhanced in the zx next to add more entry points and make them programmable. | ||
See nextreg 0xB8 - 0xBB. | See nextreg 0xB8 - 0xBB. | ||
Latest revision as of 22:55, 1 August 2026
| Port Number | $E3 |
|---|---|
| Decimal | 227 |
| Short desc. | Divmmc control |
| Bit Mask | |
| Readable | Yes |
| Writable | Yes |
| Subsystem | DIVMMC |
0xE3 Divmmc control
(R/W)
- bit 7 = conmem = 1 to map in divmmc, 0K-8K will contain the esxdos rom, 8K-16K will contain the selected divmmc bank
- bit 6 = mapram = 1 to replace the esxdos rom with divmmc bank 3
- bits 3:0 = bank = selected divmmc ram bank for 8K-16K region
- conmen can be used to manually control divmmc mapping.
- divmmc automatically maps itself in when instruction fetches hit specific addresses in the rom. When this happens, the esxdos rom (or divmmc bank 3 if mapram is set) appears in 0K-8K and the selected divmmc bank appears as ram in 8K-16K.
- bit 6 can only be set, once set only a power cycle can reset it on the original divmmc. nextreg 0x09 bit 3 can be set to reset this bit.
The divmmc has been enhanced in the zx next to add more entry points and make them programmable.
See nextreg 0xB8 - 0xBB.