Expansion Bus Decoding b0-7 Register: Difference between revisions
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core 3.1.3 changes/refresh |
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All bits are set to 1 upon hard reset. | since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is clear OR hard reset and bit 31 is set (otherwise content is kept intact). <del>All bits are set to 1 upon hard reset.</del> | ||
When the expansion bus is on, the expansion port decoding mask (Next Registers $86-$89) is logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled. | When the expansion bus is on, the expansion port decoding mask (Next Registers $86-$89) is logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled. | ||
Latest revision as of 19:02, 13 April 2020
| Next Register Number | $86 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | When expansion bus is enabled: Internal ports decoding mask |
| Bit | Description |
|---|---|
| 7 | Masking decoding: NextPort:$xx37 (also MD2 controller) |
| 6 | Masking decoding: NextPort:$xx1F (also MD1 controller) |
| 5 | Masking decoding: NextPort:$xx6B |
| 4 | Masking decoding: +3 floating bus |
| 3 | Masking decoding: NextPort:$1FFD |
| 2 | Masking decoding: NextPort:$DFFD |
| 1 | Masking decoding: NextPort:$7FFD |
| 0 | Masking decoding: NextPort:$xxFF |
since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is clear OR hard reset and bit 31 is set (otherwise content is kept intact). All bits are set to 1 upon hard reset.
When the expansion bus is on, the expansion port decoding mask (Next Registers $86-$89) is logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.
If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.
(note: Next registers with number higher than $7F are inaccessible from Copper code)