Interrupt Status 1 Register

Next Register Number	$C9
Readable	Yes
Writable	Yes
Short Description	has ctc interrupt occurred?

 bit 7 = ctc channel 7 zc/to
 bit 6 = ctc channel 6 zc/to
 bit 5 = ctc channel 5 zc/to
 bit 4 = ctc channel 4 zc/to
 bit 3 = ctc channel 3 zc/to
 bit 2 = ctc channel 2 zc/to
 bit 1 = ctc channel 1 zc/to
 bit 0 = ctc channel 0 zc/to

• (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
• (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared