Interrupt Status 0 Register: Difference between revisions
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m Xalior moved page Interrupt Status 0 to Interrupt Status 0 Register: match formal nextreg.txt name |
linking hw im2 |
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| Line 9: | Line 9: | ||
bit 0 = ULA | bit 0 = ULA | ||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending | * (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending | ||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared | * (W) Set bits clear the status. In [[hw im2 mode]] the status will continue to read as set until the interrupt pending condition is cleared | ||
Latest revision as of 20:15, 11 April 2026
| Next Register Number | $C8 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | has interrupt occurred? |
bits 7:2 = Reserved must be 0 bit 1 = Line bit 0 = ULA
- (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
- (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared