https://wiki.specnext.dev/index.php?action=history&feed=atom&title=XADC_Register 2026-05-29T18:01:52Z Revision history for this page on the wiki MediaWiki 1.43.5 https://wiki.specnext.dev/index.php?title=XADC_Register&diff=41304&oldid=prev 2025-10-14T12:48:31Z

<p>Xalior moved page <a href="/XADC_register" class="mw-redirect" title="XADC register">XADC register</a> to <a href="/XADC_Register" title="XADC Register">XADC Register</a>: match formal nextreg.txt name</p> <table style="background-color: #fff; color: #202122;" data-mw="interface"> <col class="diff-marker" /> <col class="diff-content" /> <col class="diff-marker" /> <col class="diff-content" /> <tr class="diff-title" lang="en-GB"> <td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">← Older revision</td> <td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">Revision as of 13:48, 14 October 2025</td> </tr><tr><td colspan="4" class="diff-notice" lang="en-GB"><div class="mw-diff-empty">(No difference)</div> </td></tr> <!-- diff cache key specnext_wiki:diff:1.41:old-12335:rev-41304 --> </table>

Xalior https://wiki.specnext.dev/index.php?title=XADC_Register&diff=12335&oldid=prev 2024-11-03T12:50:34Z

<p>updated to 78a6ee50</p> <p><b>New page</b></p><div>{{NextRegister<br /> |Number=$F8<br /> |Readable=Yes<br /> |Writable=Yes<br /> |ShortDesc=Issue 4 only<br /> }}<br /> bit 7 = 1 to write to XADC DRP port, 0 to read from XADC DRP port **<br /> bits 6:0 = XADC DRP register address DADDR<br /> * An XADC register read or write is initiated by writing to this register<br /> * There must be at least six 28 MHz cycles after each r/w to this register<br /> * ** Reads as 0</div>

Sol HSA