Video Line Interrupt Control Register - Revision history

Sol HSA: updated to 78a6ee50

2024-11-03T11:31:41Z

updated to 78a6ee50

← Older revision		Revision as of 12:31, 3 November 2024
Line 13:		Line 13:
	\| 6-3 \|\| Reserved, must be 0		\| 6-3 \|\| Reserved, must be 0
	\|-		\|-
	\| 2 \|\| If 1 disables original ULA interrupt (Reset to 0 after a reset)		\| 2 \|\| If 1 disables original ULA interrupt (Reset to 0 after a reset) **
	\|-		\|-
	\| 1 \|\| If 1 enables Line Interrupt (Reset to 0 after a reset)		\| 1 \|\| If 1 enables Line Interrupt (Reset to 0 after a reset) **
	\|-		\|-
	\| 0 \|\| MSB of Line Interrupt line value (Reset to 0 after a reset)		\| 0 \|\| MSB of Line Interrupt line value (Reset to 0 after a reset)
	\|}		\|}

			** Aliases of interrupt enable bits in nextreg 0xC4.

	The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.		The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.

Ped7g: core 3.1.5 changes/refresh

2020-04-27T08:22:02Z

core 3.1.5 changes/refresh

← Older revision		Revision as of 09:22, 27 April 2020
Line 23:		Line 23:

	The LSB part of desired interrupt line is in {{NextRegNo\|$23}}.		The LSB part of desired interrupt line is in {{NextRegNo\|$23}}.

			Since core 3.1.5 the numbering of lines can be offset by {{NextRegNo\|$64}}.

Ped7g: Ped7g moved page Raster Interrupt Control Register to Video Line Interrupt Control Register: sync with "nextreg.txt" terminology

2020-04-27T07:50:17Z

Ped7g moved page Raster Interrupt Control Register to Video Line Interrupt Control Register: sync with "nextreg.txt" terminology

← Older revision		Revision as of 08:50, 27 April 2020
(No difference)

Ped7g at 21:51, 31 May 2019

2019-05-31T21:51:07Z

← Older revision		Revision as of 22:51, 31 May 2019
Line 20:		Line 20:
	\|}		\|}

	The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's ~~display~~ area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt) ~~(the~~ INT signal is raised ~~when~~ horizontal position is ~~somewhere~~ between 256-319 standard pixels ~~and previous line drawing is finished). So the code in~~ interrupt handler ~~will start~~ execution ~~when~~ the ~~display beam is still in H-BLANK area and just preparing to start beaming~~ the ~~desired line~~.		The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.

	The LSB part of desired interrupt line is in {{NextRegNo\|$23}}.		The LSB part of desired interrupt line is in {{NextRegNo\|$23}}.

Specnext: 7 revisions imported

2019-04-14T10:00:20Z

7 revisions imported

← Older revision		Revision as of 11:00, 14 April 2019
(No difference)

wiki>Ped7g: further details from Jim in forum post (timing of line interrupts)

2019-01-01T18:45:45Z

further details from Jim in forum post (timing of line interrupts)

← Older revision		Revision as of 19:45, 1 January 2019
Line 19:		Line 19:
	\| 0 \|\| MSB of Line Interrupt line value (Reset to 0 after a reset)		\| 0 \|\| MSB of Line Interrupt line value (Reset to 0 after a reset)
	\|}		\|}

			The line interrupt value uses coordinate system of [https://gitlab.com/thesmog358/tbblue/blob/master/docs/extra-hw/copper/COPPER-v0.1c.TXT Copper coprocessor], i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's display area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt) (the INT signal is raised when horizontal position is somewhere between 256-319 standard pixels and previous line drawing is finished). So the code in interrupt handler will start execution when the display beam is still in H-BLANK area and just preparing to start beaming the desired line.

			The LSB part of desired interrupt line is in {{NextRegNo\|$23}}.

wiki>Ped7g at 20:09, 22 December 2018

2018-12-22T20:09:19Z

← Older revision		Revision as of 21:09, 22 December 2018
Line 8:		Line 8:
	! Bit !! Function		! Bit !! Function
	\|-		\|-
	\| 7 \|\| (R) INT ~~flag,~~ 1=~~During INT~~		\| 7 \|\| (R) INT signal (even when Z80N has interrupts disabled) (1 = interrupt is requested)
			(W) Reserved, must be 0
	\|-		\|-
	\| 6-3 \|\| Reserved, must be 0		\| 6-3 \|\| Reserved, must be 0

wiki>Emook: Added bit definitions

2018-10-20T22:48:58Z

Added bit definitions

← Older revision		Revision as of 23:48, 20 October 2018
Line 5:		Line 5:
	\|ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt.		\|ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt.
	}}		}}
			{\| class="wikitable"
			! Bit !! Function
			\|-
			\| 7 \|\| (R) INT flag, 1=During INT
			\|-
			\| 6-3 \|\| Reserved, must be 0
			\|-
			\| 2 \|\| If 1 disables original ULA interrupt (Reset to 0 after a reset)
			\|-
			\| 1 \|\| If 1 enables Line Interrupt (Reset to 0 after a reset)
			\|-
			\| 0 \|\| MSB of Line Interrupt line value (Reset to 0 after a reset)
			\|}

wiki>Hyphz at 23:23, 21 August 2017

2017-08-21T23:23:33Z

← Older revision		Revision as of 00:23, 22 August 2017
Line 3:		Line 3:
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
			\|ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt.
	}}		}}

wiki>Hyphz at 23:42, 18 August 2017

2017-08-18T23:42:22Z

← Older revision		Revision as of 00:42, 19 August 2017
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=$34		\|Number=$22
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	}}		}}