Vertical Line Count Offset Register - Revision history

Xalior: Xalior moved page Vertical Video Line Offset Register to Vertical Line Count Offset Register: match formal nextreg.txt name

2025-10-14T11:25:20Z

Xalior moved page Vertical Video Line Offset Register to Vertical Line Count Offset Register: match formal nextreg.txt name

← Older revision		Revision as of 12:25, 14 October 2025
(No difference)

Ped7g: core 3.1.5 changes/refresh

2020-04-27T19:07:06Z

core 3.1.5 changes/refresh

← Older revision		Revision as of 20:07, 27 April 2020
Line 13:		Line 13:
	Eg, if the offset is 32 then video line 32 will correspond to the first pixel row in the ULA and video line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]] (in the top border area). Then Copper WAIT command waiting for line 0 will happen already in top border area.		Eg, if the offset is 32 then video line 32 will correspond to the first pixel row in the ULA and video line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]] (in the top border area). Then Copper WAIT command waiting for line 0 will happen already in top border area.

	~~(<del>also~~ Copper mode %11 restarting CPC=0 at pixel [0,0] will be offset~~</del> - yet~~ to ~~be confirmed by Allen or VHDL source - TODO)~~		Also Copper mode %11 restarting CPC=0 at pixel [0,0] (with offset 0) will be offset to new line!

	Since a change in offset takes effect when the ULA reaches row 0, the change can take up to one frame to occur.		Since a change in offset takes effect when the ULA reaches row 0, the change can take up to one frame to occur.

	(also related: {{NextRegNo\|$1E}}, {{NextRegNo\|$1F}}, {{NextRegNo\|$22}}, {{NextRegNo\|$23}} and [[Copper]])		(also related: {{NextRegNo\|$1E}}, {{NextRegNo\|$1F}}, {{NextRegNo\|$22}}, {{NextRegNo\|$23}} and [[Copper]])

Ped7g at 08:19, 27 April 2020

2020-04-27T08:19:18Z

← Older revision		Revision as of 09:19, 27 April 2020
Line 11:		Line 11:
	Normally the ULA's pixel row 0 aligns with vertical line count 0. With a non-zero offset, the ULA's pixel row 0 will align with the vertical line offset.		Normally the ULA's pixel row 0 aligns with vertical line count 0. With a non-zero offset, the ULA's pixel row 0 will align with the vertical line offset.

	Eg, if the offset is 32 then ~~vertical~~ line 32 will correspond to the first pixel row in the ULA and ~~vertical~~ line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]] (in the top border area). Then Copper WAIT command waiting for line 0 will happen already in top border area.		Eg, if the offset is 32 then video line 32 will correspond to the first pixel row in the ULA and video line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]] (in the top border area). Then Copper WAIT command waiting for line 0 will happen already in top border area.

	(<del>also Copper mode %11 restarting CPC=0 at pixel [0,0] will be offset</del> - yet to be confirmed by Allen or VHDL source - TODO)		(<del>also Copper mode %11 restarting CPC=0 at pixel [0,0] will be offset</del> - yet to be confirmed by Allen or VHDL source - TODO)

Ped7g: core 3.1.5 changes/refresh

2020-04-27T08:06:20Z

core 3.1.5 changes/refresh

← Older revision		Revision as of 09:06, 27 April 2020
Line 11:		Line 11:
	Normally the ULA's pixel row 0 aligns with vertical line count 0. With a non-zero offset, the ULA's pixel row 0 will align with the vertical line offset.		Normally the ULA's pixel row 0 aligns with vertical line count 0. With a non-zero offset, the ULA's pixel row 0 will align with the vertical line offset.

	Eg, if the offset is 32 then vertical line 32 will correspond to the first pixel row in the ULA and vertical line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]].		Eg, if the offset is 32 then vertical line 32 will correspond to the first pixel row in the ULA and vertical line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]] (in the top border area). Then Copper WAIT command waiting for line 0 will happen already in top border area.

			(<del>also Copper mode %11 restarting CPC=0 at pixel [0,0] will be offset</del> - yet to be confirmed by Allen or VHDL source - TODO)

	Since a change in offset takes effect when the ULA reaches row 0, the change can take up to one frame to occur.		Since a change in offset takes effect when the ULA reaches row 0, the change can take up to one frame to occur.

	(also related: {{NextRegNo\|$1E}}, {{NextRegNo\|$1F}}, {{NextRegNo\|$22}}, {{NextRegNo\|$23}} and [[Copper]])		(also related: {{NextRegNo\|$1E}}, {{NextRegNo\|$1F}}, {{NextRegNo\|$22}}, {{NextRegNo\|$23}} and [[Copper]])

Ped7g: core 3.1.5 changes/refresh

2020-04-27T07:59:17Z

core 3.1.5 changes/refresh

New page

{{NextRegister
|Number=$64
|Readable=Yes
|Writable=Yes
|ShortDesc=Offset numbering of raster lines in copper/interrupt/active register
}}
Since core 3.1.5 (new register):

Bits 7-0 form offset value 0..255, the offset is added to Copper, Video Line Interrupt and Active Video Line readings.

Normally the ULA's pixel row 0 aligns with vertical line count 0. With a non-zero offset, the ULA's pixel row 0 will align with the vertical line offset.

Eg, if the offset is 32 then vertical line 32 will correspond to the first pixel row in the ULA and vertical line 0 will align with the first pixel row of the [[Tilemap]] and [[Sprites]].

Since a change in offset takes effect when the ULA reaches row 0, the change can take up to one frame to occur.

(also related: {{NextRegNo|$1E}}, {{NextRegNo|$1F}}, {{NextRegNo|$22}}, {{NextRegNo|$23}} and [[Copper]])