Tile Definitions Base Address Register - Revision history

Sol HSA: updated to 78a6ee50

2024-11-03T11:44:09Z

updated to 78a6ee50

← Older revision		Revision as of 12:44, 3 November 2024
Line 5:		Line 5:
	\|ShortDesc=Base address of the tiles' graphics.		\|ShortDesc=Base address of the tiles' graphics.
	}}		}}
	:~~bits~~ 7-6 = ~~Read back as zero~~, ~~write values ignored~~		:bit 7 = 1 to select bank 7, 0 to select bank 5
			:bit 6 = Reserved, must be 0
	:bits 5-0 = MSB of address of the tile definitions in Bank 5		:bits 5-0 = MSB of address of the tile definitions in Bank 5

	The value written is an offset into ~~Bank~~ 5 allowing [[Tilemap\|tile definitions]] to be placed at any multiple of 256 bytes.		The value written into bits 5:0 is an offset into 16K bank 5 or 8K bank 7 allowing the [[Tilemap\|tile definitions]] to be placed at any multiple of 256 bytes. The value written here can be thought of as the MSB of an address in bank 5 0x40-0x7f or bank 7 0xc0-0xff. Because bank 7 is only 8K in size, addresses wrap across the 8K boundary instead of the 16K boundary.

	~~Writing a physical~~ MSB address ~~as $40~~-~~$7F~~ or ~~$C0~~-~~$FF range~~ is ~~permitted (~~the ~~top bits will be ignored)~~.

	The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).		The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).

	Default value after soft reset corresponds to the address $4C00, i.e. default value is $0C.		Default value after soft reset corresponds to the address $4C00, i.e. default value is $0C.

Ped7g: core 3.0 changes/refresh

2019-11-12T07:26:45Z

core 3.0 changes/refresh

← Older revision		Revision as of 08:26, 12 November 2019
Line 13:		Line 13:

	The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).		The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).

			Default value after soft reset corresponds to the address $4C00, i.e. default value is $0C.

Ped7g: cross-linking with main Tilemap article

2019-05-23T05:51:07Z

cross-linking with main Tilemap article

← Older revision		Revision as of 06:51, 23 May 2019
Line 8:		Line 8:
	:bits 5-0 = MSB of address of the tile definitions in Bank 5		:bits 5-0 = MSB of address of the tile definitions in Bank 5

	The value written is an offset into Bank 5 allowing tile definitions to be placed at any multiple of 256 bytes.		The value written is an offset into Bank 5 allowing [[Tilemap\|tile definitions]] to be placed at any multiple of 256 bytes.

	Writing a physical MSB address as $40-$7F or $C0-$FF range is permitted (the top bits will be ignored).		Writing a physical MSB address as $40-$7F or $C0-$FF range is permitted (the top bits will be ignored).

	The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).		The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).

Specnext: 1 revision imported

2019-04-14T10:00:22Z

1 revision imported

← Older revision		Revision as of 11:00, 14 April 2019
(No difference)

wiki>Ped7g: Core 2.00.26 changes

2019-01-31T19:52:49Z

Core 2.00.26 changes

New page

{{NextRegister
|Number=$6F
|Readable=Yes
|Writable=Yes
|ShortDesc=Base address of the tiles' graphics.
}}
:bits 7-6 = Read back as zero, write values ignored
:bits 5-0 = MSB of address of the tile definitions in Bank 5

The value written is an offset into Bank 5 allowing tile definitions to be placed at any multiple of 256 bytes.

Writing a physical MSB address as $40-$7F or $C0-$FF range is permitted (the top bits will be ignored).

The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $EB the read of this register will produce value $2B (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).