Reset Register - Revision history

Xalior: Xalior moved page Next Reset Register to Reset Register: match formal nextreg.txt name

2025-10-13T17:04:07Z

Xalior moved page Next Reset Register to Reset Register: match formal nextreg.txt name

← Older revision		Revision as of 18:04, 13 October 2025
(No difference)

Johnnyo: adding bit 7 for write

2025-04-22T20:32:32Z

adding bit 7 for write

← Older revision		Revision as of 21:32, 22 April 2025
Line 15:		Line 15:
	* Only one of bits 1:0 will be set		* Only one of bits 1:0 will be set
	Write:		Write:
			bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)
	bits 6:5 = Reserved must be zero		bits 6:5 = Reserved must be zero
	bit 4 = Clear i/o trap (write zero to clear) (experimental) **		bit 4 = Clear i/o trap (write zero to clear) (experimental) **

Sol HSA: updated to 78a6ee50

2024-11-03T10:46:27Z

updated to 78a6ee50

← Older revision		Revision as of 11:46, 3 November 2024
Line 6:		Line 6:
	}}		}}
	Read:		Read:
	bit 7 = ~~Indicates~~ the reset signal to the expansion bus and esp is asserted		bit 7 = 1 if the reset signal to the expansion bus and esp is asserted
	bits 6:2 = ~~Reserved~~		bits 6:5 = Reserved
	bit 1 = ~~Indicates~~ the last reset was a hard reset		bit 4 = 1 if multiface nmi was generated by an i/o trap (experimental, see nextreg 0xda)
	bit 0 = ~~Indicates~~ the last reset was a soft reset		bit 3 = 1 if multiface nmi was generated by this nextreg
			bit 2 = 1 if divmmc nmi was generated by this nextreg
			bit 1 = 1 if the last reset was a hard reset
			bit 0 = 1 if the last reset was a soft reset
	* Only one of bits 1:0 will be set		* Only one of bits 1:0 will be set
	Write:		Write:
	~~bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)~~		bits 6:5 = Reserved must be zero
	bits 6:4 = Reserved, must be 0		bit 4 = Clear i/o trap (write zero to clear) (experimental) **
	bit 3 = ~~Trigger NMI debugger on NextZXOS~~		bit 3 = Generate multiface nmi (write zero to clear) **
	bit 2 = ~~Must be 0~~		bit 2 = Generate divmmc nmi (write zero to clear) **
	bit 1 = Generate a hard reset (reboot)		bit 1 = Generate a hard reset (reboot) *
	bit 0 = Generate a soft reset		bit 0 = Generate a soft reset *
	* Hard reset has precedence		* Hard reset has precedence
			** These signals are ignored if the multiface, divmmc, dma or external nmi master is active
			** Copper cannot clear these bits
			** An i/o trap could occur at the same time as mf / divmmc cause; always check this bit in nmi isr if important


	A useful NEXTREG 2, 8 will trigger the NextZXOS debugger status page, a hardware breakpoint.		A useful NEXTREG 2, 8 will trigger the NextZXOS debugger status page, a hardware breakpoint.

Em00k at 23:14, 17 March 2023

2023-03-17T23:14:56Z

← Older revision		Revision as of 00:14, 18 March 2023
Line 19:		Line 19:
	bit 0 = Generate a soft reset		bit 0 = Generate a soft reset
	* Hard reset has precedence		* Hard reset has precedence

			A useful NEXTREG 2, 8 will trigger the NextZXOS debugger status page, a hardware breakpoint.

Em00k at 23:13, 17 March 2023

2023-03-17T23:13:44Z

← Older revision		Revision as of 00:13, 18 March 2023
Line 13:		Line 13:
	Write:		Write:
	bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)		bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)
	bits 6:2 = Reserved, must be 0		bits 6:4 = Reserved, must be 0
			bit 3 = Trigger NMI debugger on NextZXOS
			bit 2 = Must be 0
	bit 1 = Generate a hard reset (reboot)		bit 1 = Generate a hard reset (reboot)
	bit 0 = Generate a soft reset		bit 0 = Generate a soft reset
	* Hard reset has precedence		* Hard reset has precedence

Ped7g: core 3.0 changes

2019-11-11T11:32:17Z

core 3.0 changes

← Older revision		Revision as of 12:32, 11 November 2019
Line 5:		Line 5:
	\|ShortDesc=Identifies type of last reset. Can be written to force reset.		\|ShortDesc=Identifies type of last reset. Can be written to force reset.
	}}		}}
	~~{\| class~~=~~"wikitable"~~		Read:
	~~! Bit~~		bit 7 = Indicates the reset signal to the expansion bus and esp is asserted
	~~! Function~~		bits 6:2 = Reserved
	\|-		bit 1 = Indicates the last reset was a hard reset
	\| 7 ~~\|\| Reserved~~ (~~write~~ 0)		bit 0 = Indicates the last reset was a soft reset
	\|-		* Only one of bits 1:0 will be set
	\| 6 \|\| Reserved		Write:
	\|-		bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0)
	~~\| 5 \|\| Reserved~~		bits 6:2 = Reserved, must be 0
	\|-		bit 1 = Generate a hard reset (reboot)
	~~\| 4 \|\| Reserved~~		bit 0 = Generate a soft reset
	\|-		* Hard reset has precedence
	~~\| 3 \|\| Reserved~~
	\|-
	~~\| 2 \|\| Read-only~~, ~~indicates power-on reset~~
	\|-
	\| 1 ~~\|\| Indicates hard reset. Writing 1 causes~~ a hard reset.
	\|-
	\| 0 ~~\|\| Indicates soft reset. Writing 1 causes~~ a soft reset.
	\|}

Specnext: 9 revisions imported

2019-04-14T10:00:19Z

9 revisions imported

← Older revision	Revision as of 11:00, 14 April 2019
(No difference)

wiki>Ped7g: Fix bit value typo

2018-12-20T14:17:43Z

Fix bit value typo

← Older revision		Revision as of 15:17, 20 December 2018
Line 9:		Line 9:
	! Function		! Function
	\|-		\|-
	\| 7 \|\| Reserved		\| 7 \|\| Reserved (write 0)
	\|-		\|-
	\| 6 \|\| Reserved		\| 6 \|\| Reserved
Line 23:		Line 23:
	\| 1 \|\| Indicates hard reset. Writing 1 causes a hard reset.		\| 1 \|\| Indicates hard reset. Writing 1 causes a hard reset.
	\|-		\|-
	\| 0 \|\| Indicates soft reset. Writing 0 causes a soft reset.		\| 0 \|\| Indicates soft reset. Writing 1 causes a soft reset.
	\|}		\|}

wiki>Hyphz at 23:37, 18 August 2017

2017-08-18T23:37:45Z

← Older revision		Revision as of 00:37, 19 August 2017
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=2		\|Number=$02
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes

wiki>Hyphz at 23:37, 18 August 2017

2017-08-18T23:37:34Z

← Older revision		Revision as of 00:37, 19 August 2017
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=~~$02~~		\|Number=2
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes