Peripheral 3 Setting Register - Revision history

Xalior: Xalior moved page Peripheral 3 Register to Peripheral 3 Setting Register: match formal nextreg.txt name

2025-10-13T14:47:34Z

Xalior moved page Peripheral 3 Register to Peripheral 3 Setting Register: match formal nextreg.txt name

← Older revision		Revision as of 15:47, 13 October 2025
(No difference)

Ped7g at 00:05, 16 April 2020

2020-04-16T00:05:08Z

← Older revision		Revision as of 01:05, 16 April 2020
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	bit 4 = Enable internal speaker (hard reset = 1)		bit 4 = Enable internal speaker (hard reset = 1)
	bit 3 = Enable 8-bit DACs (A,B,C,D) (hard reset = 0)		bit 3 = Enable 8-bit DACs (A,B,C,D) (hard reset = 0)
	bit 2 = Enable port $FF Timex video mode read (~~disables~~ floating bus on 0xff) (hard reset = 0)		bit 2 = Enable port $FF Timex video mode read (hides floating bus on 0xff) (hard reset = 0)
	bit 1 = Enable Turbosound (currently selected AY is frozen when disabled) (hard reset = 0)		bit 1 = Enable Turbosound (currently selected AY is frozen when disabled) (hard reset = 0)
	bit 0 = Implement Issue 2 keyboard (port $FE reads as early ZX boards) (hard reset = 0)		bit 0 = Implement Issue 2 keyboard (port $FE reads as early ZX boards) (hard reset = 0)

Ped7g: core 3.0 changes/refresh

2019-12-02T19:44:13Z

core 3.0 changes/refresh

← Older revision		Revision as of 20:44, 2 December 2019
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	}}		}}
	(R/W) 0x08 (08) => Peripheral 3 setting:		(R/W) 0x08 (08) => Peripheral 3 setting:
	bit 7 = Unlock(1)/lock(0) port $7FFD (read 1 indicates port $7FFD is not locked)		bit 7 = Unlock(1)/lock(0) port $7FFD paging (read 1 indicates port $7FFD is not locked)
	bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0)		bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0)
	bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0)		bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0)
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	The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.		The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.

	When loading 48k SNA files through NextZXOS, be aware it does lock down many features of Next to better simulate ZX48 machine, including lock of $7FFD ~~port~~. If you are using 48k SNA file for convenience, but you are actually using full ZX Next features, make sure you enable/unlock all relevant bits, before using the particular feature.		When loading 48k SNA files through NextZXOS, be aware it does lock down many features of Next to better simulate ZX48 machine, including lock of {{PortNo\|$7FFD}} paging feature. If you are using 48k SNA file for convenience, but you are actually using full ZX Next features, make sure you enable/unlock all relevant bits, before using the particular feature.

Ped7g: core 3.0 changes/refresh

2019-12-02T19:36:12Z

core 3.0 changes/refresh

← Older revision		Revision as of 20:36, 2 December 2019
Line 6:		Line 6:
	}}		}}
	(R/W) 0x08 (08) => Peripheral 3 setting:		(R/W) 0x08 (08) => Peripheral 3 setting:
	bit 7 = Unlock(1)/lock(0) port $7FFD ~~bit 5~~ (read 1 indicates port $7FFD is not locked)		bit 7 = Unlock(1)/lock(0) port $7FFD (read 1 indicates port $7FFD is not locked)
	bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0)		bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0)
	bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0)		bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0)
Line 16:		Line 16:

	The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.		The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.

			When loading 48k SNA files through NextZXOS, be aware it does lock down many features of Next to better simulate ZX48 machine, including lock of $7FFD port. If you are using 48k SNA file for convenience, but you are actually using full ZX Next features, make sure you enable/unlock all relevant bits, before using the particular feature.

Ped7g: core 3.0 changes/refresh

2019-11-11T15:52:07Z

core 3.0 changes/refresh

← Older revision		Revision as of 16:52, 11 November 2019
Line 16:		Line 16:

	The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.		The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.

	~~'''NEW in core 3.0:'''~~

	~~bit 4 default 0~~
	- needs clarification from core team, two documents about core3.0 registers I have available contradict each other, but I guess the "0" is the correct default and the "1" in table above is obsolete setting.

Ped7g: core 3.0 changes/refresh

2019-11-11T12:28:55Z

core 3.0 changes/refresh

← Older revision		Revision as of 13:28, 11 November 2019
Line 6:		Line 6:
	}}		}}
	(R/W) 0x08 (08) => Peripheral 3 setting:		(R/W) 0x08 (08) => Peripheral 3 setting:
	bit 7 = ~~128K paging enable~~ (~~inverse of~~ port ~~0x7ffd,~~ bit 5)		bit 7 = Unlock(1)/lock(0) port $7FFD bit 5 (read 1 indicates port $7FFD is not locked)
	~~Unlike the paging lock in~~ port ~~0x7ffd,~~		bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0)
	~~this may be enabled or disabled at any time.~~		bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0)
	~~Use "1" to disable the~~ locked ~~paging.~~		bit 4 = Enable internal speaker (hard reset = 1)
	bit 6 = "1" to disable RAM contention. (0 ~~after a reset~~)		bit 3 = Enable 8-bit DACs (A,B,C,D) (hard reset = 0)
	bit 5 = ~~Stereo~~ mode (0 = ABC, 1 = ACB)(0 ~~after a PoR or Hard-reset~~)		bit 2 = Enable port $FF Timex video mode read (disables floating bus on 0xff) (hard reset = 0)
	bit 4 = Enable internal speaker (1 = ~~enabled)(~~1 ~~after a PoR or Hard-reset~~)		bit 1 = Enable Turbosound (currently selected AY is frozen when disabled) (hard reset = 0)
	bit 3 = Enable ~~Specdrum/Covox~~ (~~1 = enabled~~)(0 ~~after a PoR or Hard-reset~~)		bit 0 = Implement Issue 2 keyboard (port $FE reads as early ZX boards) (hard reset = 0)
	bit 2 = ~~Make~~ $FF Timex ~~port readable~~ (~~covers "~~floating bus") (0 ~~after a PoR or Hard-reset~~)
	bit 1 = Enable ~~TurboSound~~ (~~1 = enabled~~)(0 ~~after a PoR or Hard-reset~~)
	bit 0 = ~~(core 3.0) Selects issue~~ 2 keyboard (port $FE reads as early ZX boards)

	~~https://www.specnext.com/tbblue-io-port-system/~~

	The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.		The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.
Line 25:		Line 20:

	bit 4 default 0		bit 4 default 0
	~~bit~~ 0 ~~set selects issue 2 keyboard~~		- needs clarification from core team, two documents about core3.0 registers I have available contradict each other, but I guess the "0" is the correct default and the "1" in table above is obsolete setting.

Ped7g: core 3.0 changes

2019-10-04T15:14:46Z

core 3.0 changes

← Older revision		Revision as of 16:14, 4 October 2019
Line 16:		Line 16:
	bit 2 = Make $FF Timex port readable (covers "floating bus") (0 after a PoR or Hard-reset)		bit 2 = Make $FF Timex port readable (covers "floating bus") (0 after a PoR or Hard-reset)
	bit 1 = Enable TurboSound (1 = enabled)(0 after a PoR or Hard-reset)		bit 1 = Enable TurboSound (1 = enabled)(0 after a PoR or Hard-reset)
	bit 0 = (core 3.0) Selects issue 2 keyboard		bit 0 = (core 3.0) Selects issue 2 keyboard (port $FE reads as early ZX boards)

	https://www.specnext.com/tbblue-io-port-system/		https://www.specnext.com/tbblue-io-port-system/

Ped7g at 15:12, 4 October 2019

2019-10-04T15:12:50Z

← Older revision		Revision as of 16:12, 4 October 2019
Line 19:		Line 19:

	https://www.specnext.com/tbblue-io-port-system/		https://www.specnext.com/tbblue-io-port-system/

			The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.

	'''NEW in core 3.0:'''		'''NEW in core 3.0:'''

Ped7g: wording/style polish

2019-10-04T14:36:01Z

wording/style polish

← Older revision		Revision as of 15:36, 4 October 2019
Line 14:		Line 14:
	bit 4 = Enable internal speaker (1 = enabled)(1 after a PoR or Hard-reset)		bit 4 = Enable internal speaker (1 = enabled)(1 after a PoR or Hard-reset)
	bit 3 = Enable Specdrum/Covox (1 = enabled)(0 after a PoR or Hard-reset)		bit 3 = Enable Specdrum/Covox (1 = enabled)(0 after a PoR or Hard-reset)
	bit 2 = ~~Enable~~ Timex ~~modes~~ (~~1 = enabled~~)(0 after a PoR or Hard-reset)		bit 2 = Make $FF Timex port readable (covers "floating bus") (0 after a PoR or Hard-reset)
	bit 1 = Enable TurboSound (1 = enabled)(0 after a PoR or Hard-reset)		bit 1 = Enable TurboSound (1 = enabled)(0 after a PoR or Hard-reset)
	bit 0 = ~~Reserved, must be~~ 0		bit 0 = (core 3.0) Selects issue 2 keyboard

	https://www.specnext.com/tbblue-io-port-system/		https://www.specnext.com/tbblue-io-port-system/

Ped7g at 05:59, 4 October 2019

2019-10-04T05:59:15Z

← Older revision		Revision as of 06:59, 4 October 2019
Line 22:		Line 22:
	'''NEW in core 3.0:'''		'''NEW in core 3.0:'''

	bit 4 default 0		bit 4 default 0
	bit 0 set selects issue 2 keyboard		bit 0 set selects issue 2 keyboard