Layer 2 - Revision history

Johnnyo: rewording

2026-05-20T00:39:10Z

rewording

← Older revision		Revision as of 01:39, 20 May 2026
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	The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.		The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.

	The Layer 2 screen occupies 48kiB or 80kiB, ~~which is stored in~~ 3 (or 5) consecutive 16K [[Memory map\|banks]]. By NextZXOS/NextBASIC default, the same banks 9-11 are used for both the visible and "shadow" Layer 2 screen (the core, after power-on but before the NextZXOS boots set its defaults to 8-10 for the displayed Layer 2 screen and 11-13 for the shadow screen, but these settings are modified during the boot of NextZXOS). The starting bank of the main Layer 2 screen can be changed using {{NextRegNo\|$12}} and and the starting bank for the shadow Layer 2 screen can be changed using {{NextRegNo\|$13}} (avoid using banks 5, 7 and 8 for the Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).		The Layer 2 screen occupies 48kiB or 80kiB, spreading over 3, or 5, consecutive 16K [[Memory map\|banks]]. By the NextZXOS/NextBASIC default, the same banks 9-11 are used for both the visible and the "shadow" Layer 2 screen (the core, after power-on but before the NextZXOS boots set its defaults to 8-10 for the displayed Layer 2 screen and 11-13 for the shadow screen, but these settings are modified during the boot of NextZXOS). The starting bank of the main Layer 2 screen can be changed using {{NextRegNo\|$12}} and and the starting bank for the shadow Layer 2 screen can be changed using {{NextRegNo\|$13}} (avoid using banks 5, 7 and 8 for the Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.		Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.

Johnnyo: rewording starting REG 12 / 13

2026-05-20T00:37:52Z

rewording starting REG 12 / 13

← Older revision		Revision as of 01:37, 20 May 2026
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	The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.		The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.

	The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive 16K [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but ~~that gets~~ modified by NextZXOS ~~booting up~~). The starting bank of the main Layer 2 screen can be changed using {{NextRegNo\|$12}} and and the starting bank for the shadow Layer 2 screen can be changed using {{NextRegNo\|$13}} (avoid using banks 5, 7 and 8 for the Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive 16K [[Memory map\|banks]]. By NextZXOS/NextBASIC default, the same banks 9-11 are used for both the visible and "shadow" Layer 2 screen (the core, after power-on but before the NextZXOS boots set its defaults to 8-10 for the displayed Layer 2 screen and 11-13 for the shadow screen, but these settings are modified during the boot of NextZXOS). The starting bank of the main Layer 2 screen can be changed using {{NextRegNo\|$12}} and and the starting bank for the shadow Layer 2 screen can be changed using {{NextRegNo\|$13}} (avoid using banks 5, 7 and 8 for the Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.		Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.

Johnnyo: wording re starting banks

2026-05-20T00:32:54Z

wording re starting banks

← Older revision		Revision as of 01:32, 20 May 2026
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	The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.		The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.

	The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). ~~These~~ can be ~~set~~ using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 ~~to be used as~~ Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive 16K [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). The starting bank of the main Layer 2 screen can be changed using {{NextRegNo\|$12}} and and the starting bank for the shadow Layer 2 screen can be changed using {{NextRegNo\|$13}} (avoid using banks 5, 7 and 8 for the Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.		Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.

Johnnyo: half a byte

2026-05-07T15:46:33Z

half a byte

← Older revision		Revision as of 16:46, 7 May 2026
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	The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or a ~~half~~ byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.		Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or half a byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.

	Layer 2 is controlled via {{PortNo\|$123B}} and {{NextRegNo\|$70}}, the port is bit mapped as follows:		Layer 2 is controlled via {{PortNo\|$123B}} and {{NextRegNo\|$70}}, the port is bit mapped as follows:

Johnnyo: rewording

2026-05-06T13:38:24Z

rewording

← Older revision		Revision as of 14:38, 6 May 2026
Line 5:		Line 5:
	The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	Each pixel of Layer 2 ~~is assigned 1~~ byte of video memory (in 8bpp modes~~). This means~~ Layer 2 ~~consumes a total of~~ 48kiB (256x192) or 80kiB (320x256). ~~Since the Spectrum banks are 16kiB,~~ Layer 2 256x192 mode is divided horizontally into 3 banks of 64 lines each~~, each of which is exactly 16kiB~~. The ~~mode~~ 320x256 (and 640x256~~) is~~ divided vertically into 5 banks of 64 (128) columns each.		Each pixel of Layer 2 takes one byte of video memory in 8bpp modes or a half byte in 4bpp mode, so the Layer 2 needs 48kiB for 256x192 mode or 80kiB for 320x256-8bit or 640x256-4bit mode. The Layer 2 256x192 mode is divided '''horizontally''' into 3 16kiB banks of 64 '''lines''' each. The modes 320x256 and 640x256 are divided '''vertically''' into 5 16kiB banks of 64 '''columns''' each for 320x256 mode or 128 '''columns''' each for 640x256 mode.

	Layer 2 is controlled via {{PortNo\|$123B}} and {{NextRegNo\|$70}}, the port is bit mapped as follows:		Layer 2 is controlled via {{PortNo\|$123B}} and {{NextRegNo\|$70}}, the port is bit mapped as follows:

Johnnyo: palette detail

2026-05-04T13:40:39Z

palette detail

← Older revision		Revision as of 14:40, 4 May 2026
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	Layer 2 provides an additional screen layer at 256x192 256 colours, 320x256 256 colours or 640x256 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated/Tilemap layer.		Layer 2 provides an additional screen layer at 256x192 256 colours, 320x256 256 colours or 640x256 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated/Tilemap layer.

			The palette used to show the Layer 2 is selected by the bit 2 of the {{NextRegNo\|$43}}.

	The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

Varmfskii: size of hidden memory

2020-11-19T20:03:15Z

size of hidden memory

← Older revision		Revision as of 21:03, 19 November 2020
Line 30:		Line 30:
	With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).		With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).

	Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+~~4kiB~~ of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8 (and avoid also Bank 8, unless you want to destroy NextBASIC warm-restart/soft-reset variables).		Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 16+8kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8 (and avoid also Bank 8, unless you want to destroy NextBASIC warm-restart/soft-reset variables).

	Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).		Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).

Ped7g: refresh with core 3.1.5 stuff

2020-11-19T18:09:57Z

refresh with core 3.1.5 stuff

← Older revision		Revision as of 19:09, 19 November 2020
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	Layer 2 provides an additional screen layer at ~~256192~~ 256 colours, ~~320240~~ 256 colours or ~~640 * 512~~ 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated ~~screen~~ / Tilemap. ~~Information for selecting the resolution and banks can be found on NextReg $70 https://wiki.specnext.dev/Layer_2_Control_Register~~		Layer 2 provides an additional screen layer at 256x192 256 colours, 320x256 256 colours or 640x256 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated/Tilemap layer.

	~~Since core~~ 3.0 the visible Layer 2 ~~will not cause~~ the ~~slow down of CPU~~, ~~even in 14MHz~~ and ~~28MHz modes~~, ~~the machine will operate at same speed~~ as ~~when~~ Layer 2 ~~is invisible~~.		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	~~'''~~This ~~page~~ is ~~updated core2.0 info with core~~ 3.~~0 changes, but may still lack some detail or contain some inaccuracy~~.~~'''~~		Each pixel of Layer 2 is assigned 1 byte of video memory (in 8bpp modes). This means Layer 2 consumes a total of 48kiB (256x192) or 80kiB (320x256). Since the Spectrum banks are 16kiB, Layer 2 256x192 mode is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16kiB. The mode 320x256 (and 640x256) is divided vertically into 5 banks of 64 (128) columns each.

	~~The~~ Layer 2 ~~screen occupies 48kiB, which~~ is ~~stored in 3 consecutive [[Memory map\|banks]]. By default, banks 8-10 are used for the visible Layer 2 screen and banks 11-13 for the shadow Layer 2 screen. These can be set using~~ {{~~NextRegNo~~\|$12}} and {{NextRegNo\|$13}} ~~(avoid banks 5 and 7 to be used as Layer 2 screen~~, ~~unless you are familiar with SRAM and BRAM of the board and how~~ the ~~ULA screen memory has special treatment in Next's FPGA).~~		Layer 2 is controlled via {{PortNo\|$123B}} and {{NextRegNo\|$70}}, the port is bit mapped as follows:

	Each pixel of Layer 2 is assigned 1 byte of video memory. This means Layer 2 consumes a total of 48kiB. Since the Spectrum banks are 16kiB, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16kiB.

	~~Layer 2 is controlled via {{PortNo\|$123B}}, which~~ is bit mapped as follows:

	{\| class="wikitable"		{\| class="wikitable"
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	With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).		With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).

	Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8.		Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8 (and avoid also Bank 8, unless you want to destroy NextBASIC warm-restart/soft-reset variables).

	Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).		Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).

			There is one more new functionality in latest 3.x cores, allowing to set bank-offset variable from 0 to 7. This offset is further applied to the bank selected for write/read (by writing value 0..7 to the port with bit4 set (so it's value 16..23). If you did set for example 16kiB write mapping of first bank, the first bank is 9, and use value 21 for bank-offset setup (+5 offset), the bank mapped into $0000..$3FFF address area will be 14 (9+5). This way you can map full 80kiB of pixel data into the bottom 16kiB window (or bottom 48kiB window), using different offsets.

			Use {{NextRegNo\|$70}} to select particular Layer2 mode, and to modify palette offset (added to top four bits of each pixel). Don't forget to set up Layer 2 clip window correctly for each mode ({{NextRegNo\|$18}}).

	You can still use also the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000 (or use the ZX Next MMU registers to map that RAM in other regions). This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.		You can still use also the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000 (or use the ZX Next MMU registers to map that RAM in other regions). This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.

	Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.		Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels in 256x192 mode are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.

			In mode 320x256 (8bpp) the pixels are stored in memory going from top to bottom and left to right (second byte is first pixel on second line, 256th byte is second pixel on first line). Since there are 256 pixels per column, the upper byte of address could represent the X coordinate (only specific range of them, as whole 0..319 range does not fit into 8 bits), and the lower byte of address is Y coordinate. The total pixel memory is 80kiB (five 16kiB banks), and could be mapped into memory either by MMU or by bank-offset feature of {{PortNo\|$123B}}.

			In mode 640x256 (4bpp) the pixels are stored identically to 320x256 mode, but every byte contains two pixels. The top nibble (top four bits) form "left" pixel, and the bottom nibble form "right" pixel, so first 256 bytes will display as two columns on screen, not one.

	Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.		Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.

	System registers {{NextRegNo\|$16}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer		System registers {{NextRegNo\|$16}}, {{NextRegNo\|$71}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer
	2, allowing scrolling effects to be created.		2, allowing scrolling effects to be created.

	Since core 3.0 the visibility of Layer 2 is not affected by usage of ZX128 ULA-shadow (Bank 7) screen.		Since core 3.0 the visibility of Layer 2 is not affected by usage of ZX128 ULA-shadow (Bank 7) screen.

			Obsolete info for core 2.x (limitation was lifted in core 3.0): <del>the visible Layer 2 will cause the slow down of CPU to 7MHz.</del>

	To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM paging functionality ({{PortNo\|$123B}}).		To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM paging functionality ({{PortNo\|$123B}}).

Em00k: added extra resolutions

2020-11-18T19:35:34Z

added extra resolutions

← Older revision		Revision as of 20:35, 18 November 2020
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	Layer 2 is an additional ~~graphics feature on the Next. It provides a 256-color~~ screen at ~~the full 256x192 resolution~~, in which every pixel is individually ~~colored~~. Layer 2 may appear in place of, behind, or above the ULA-generated screen.		Layer 2 provides an additional screen layer at 256192 256 colours, 320240 256 colours or 640 * 512 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated screen / Tilemap. Information for selecting the resolution and banks can be found on NextReg $70 https://wiki.specnext.dev/Layer_2_Control_Register

	Since core 3.0 the visible Layer 2 will not cause the slow down of CPU, even in 14MHz and 28MHz modes, the machine will operate at same speed as when Layer 2 is invisible.		Since core 3.0 the visible Layer 2 will not cause the slow down of CPU, even in 14MHz and 28MHz modes, the machine will operate at same speed as when Layer 2 is invisible.

Ped7g: core 3.0 changes/refresh

2019-11-27T16:59:00Z

core 3.0 changes/refresh

← Older revision		Revision as of 17:59, 27 November 2019
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	\|-		\|-
	\| 1 \|\| Layer 2 visible - {{NextRegNo\|$12}}		\| 1 \|\| Layer 2 visible - {{NextRegNo\|$12}}
			Since core 3.0 this bit has mirror in {{NextRegNo\|$69}}
	\|-		\|-
	\| 0 \|\| Enable Layer 2 write-only paging		\| 0 \|\| Enable Layer 2 write-only paging