Interrupt Control Register - Revision history

Johnnyo: add the link to the hw im2 mode

2026-04-11T19:11:17Z

add the link to the hw im2 mode

← Older revision		Revision as of 20:11, 11 April 2026
Line 23:		Line 23:
	bit 0 = 0		bit 0 = 0

	* * In hw im2 mode the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 0xFF is generated.		* * In [[hw im2 mode]] the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 0xFF is generated.

	* ** The return address pushed during an nmi acknowledge cycle will be written to nextreg instead of memory (the stack pointer will be decremented) and the first RETN after the acknowledge will take its return address from nextreg instead of memory (the stack pointer will be incremented). If bit 3 = 0 and in other circumstances, RETN functions normally.		* ** The return address pushed during an nmi acknowledge cycle will be written to nextreg instead of memory (the stack pointer will be decremented) and the first RETN after the acknowledge will take its return address from nextreg instead of memory (the stack pointer will be incremented). If bit 3 = 0 and in other circumstances, RETN functions normally.

Xalior: Xalior moved page Interrupt Control to Interrupt Control Register: match formal nextreg.txt name

2025-10-14T12:39:25Z

Xalior moved page Interrupt Control to Interrupt Control Register: match formal nextreg.txt name

← Older revision		Revision as of 13:39, 14 October 2025
(No difference)

Sol HSA: updated to 78a6ee50

2024-11-03T12:17:22Z

updated to 78a6ee50

New page

{{NextRegister
|Number=$C0
|Readable=Yes
|Writable=Yes
}}
Soft reset = 0x00

bits 7:5 = Programmable portion of im2 vector*
bit 4 = Reserved must be 0
bit 3 = Enable stackless nmi response**
bits 2:1 = Current Z80 interrupt mode 0,1,2 (read only, write ignored)
bit 0 = Maskable interrupt mode: pulse (0) or hw im2 mode (1)

* * In hw im2 mode the interrupt vector generated is:
bits 7:5 = nextreg 0xC0 bits 7:5
bits 4:1 = 0 line interrupt (highest priority)
= 1 uart0 Rx
= 2 uart1 Rx
= 3-10 ctc channels 0-7
= 11 ula
= 12 uart0 Tx
= 13 uart1 Tx (lowest priority)
bit 0 = 0

* * In hw im2 mode the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 0xFF is generated.

* ** The return address pushed during an nmi acknowledge cycle will be written to nextreg instead of memory (the stack pointer will be decremented) and the first RETN after the acknowledge will take its return address from nextreg instead of memory (the stack pointer will be incremented). If bit 3 = 0 and in other circumstances, RETN functions normally.