GPIO Socket (J15) - Revision history

Sol HSA: gallerize images

2025-10-07T14:47:53Z

gallerize images

← Older revision		Revision as of 15:47, 7 October 2025
Line 10:		Line 10:
	The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.		The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.

	~~[[Image:~~NEXT GPIO location.jpg~~\|thumb~~\|J15 position on circuit board]]		<gallery>
	~~[[Image:~~NEXT_GPIO.png~~\|thumb~~\|GPIO pinout image]]		NEXT GPIO location.jpg\|J15 position on circuit board
			NEXT_GPIO.png\|GPIO pinout image
			</gallery>

	In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. This is factory fitted on 2B boards with a two slot connector for the additional two lines on a third membrane tail. The extra data is handled by the VHDL in the FPGA so it still appears as a standard 48K Membrane but, without the complexity of three layers needed.		In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. This is factory fitted on 2B boards with a two slot connector for the additional two lines on a third membrane tail. The extra data is handled by the VHDL in the FPGA so it still appears as a standard 48K Membrane but, without the complexity of three layers needed.

	This change does mean it is slightly harder to use J15 as the socket overlaps some ajoining holes slightly.		This change does mean it is slightly harder to use J15 as the socket overlaps some ajoining holes slightly.

Timgilberts at 21:36, 4 March 2020

2020-03-04T21:36:37Z

← Older revision		Revision as of 22:36, 4 March 2020
Line 13:		Line 13:
	[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]		[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]

	In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. ~~Final specs have not yet been finalised~~.		In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. This is factory fitted on 2B boards with a two slot connector for the additional two lines on a third membrane tail. The extra data is handled by the VHDL in the FPGA so it still appears as a standard 48K Membrane but, without the complexity of three layers needed.

			This change does mean it is slightly harder to use J15 as the socket overlaps some ajoining holes slightly.

Daz: FPGA page link

2019-07-04T13:11:07Z

FPGA page link

← Older revision		Revision as of 14:11, 4 July 2019
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	* I2C serial protocol		* I2C serial protocol
	* UART		* UART
	* Spare pins on the FPGA		* Spare pins on the [[FPGA]]
	* 5v, 3.3v and GND		* 5v, 3.3v and GND

Daz: Added links

2019-07-04T12:59:34Z

Added links

← Older revision		Revision as of 13:59, 4 July 2019
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	* 5v, 3.3v and GND		* 5v, 3.3v and GND

	The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.		The UART is also used for the [[ESP8266-01\|ESP Wi-fi module]], and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the [[RTC\|real time clock]] module.

	The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.		The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.

Phoebus at 12:02, 25 June 2019

2019-06-25T12:02:25Z

← Older revision		Revision as of 13:02, 25 June 2019
Line 8:		Line 8:
	The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.		The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.

	The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down ~~resisters~~ may be required for some pins to limit current.		The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.

	[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]		[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]

Phoebus at 11:52, 25 June 2019

2019-06-25T11:52:47Z

← Older revision		Revision as of 12:52, 25 June 2019
Line 13:		Line 13:
	[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]		[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]

	In June 2019 it was announced that ~~two~~ pins of J15 would be used for two additional keyboard connections on full cased Nexts. Final specs have not yet been finalised.		In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. Final specs have not yet been finalised.

Daz: Keyboard pins heads-up

2019-06-24T20:39:50Z

Keyboard pins heads-up

← Older revision		Revision as of 21:39, 24 June 2019
Line 12:		Line 12:
	[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]		[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]
	[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]		[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]

			In June 2019 it was announced that two pins of J15 would be used for two additional keyboard connections on full cased Nexts. Final specs have not yet been finalised.

Daz: Added J15 header info

2019-06-20T15:24:48Z

Added J15 header info

← Older revision		Revision as of 16:24, 20 June 2019
Line 8:		Line 8:
	The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.		The UART is also used for the ESP Wi-fi module, and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the real time clock module.

	The GPIO is not populated and requires a socket to be installed. Pull up/down resisters may be required for some pins to limit current.		The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resisters may be required for some pins to limit current.

	[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]		[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]
	[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]		[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]

Daz at 14:06, 19 June 2019

2019-06-19T14:06:16Z

← Older revision		Revision as of 15:06, 19 June 2019
Line 11:		Line 11:

	[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]		[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]
	[[Image:~~https://www~~.~~specnext.com/forum/download/file.php?id=403~~\|thumb\|GPIO pinout image ~~(from SpecNext.com forums)~~]]		[[Image:NEXT_GPIO.png\|thumb\|GPIO pinout image]]

Daz: Image links

2019-06-19T13:42:51Z

Image links

← Older revision		Revision as of 14:42, 19 June 2019
Line 10:		Line 10:
	The GPIO is not populated and requires a socket to be installed. Pull up/down resisters may be required for some pins to limit current.		The GPIO is not populated and requires a socket to be installed. Pull up/down resisters may be required for some pins to limit current.

	~~<gallery>~~		[[Image:NEXT GPIO location.jpg\|thumb\|J15 position on circuit board]]
	https://www.specnext.com/forum/download/file.php?id=403\|~~J15~~ pinout image (from SpecNext.com forums)		[[Image:https://www.specnext.com/forum/download/file.php?id=403\|thumb\|GPIO pinout image (from SpecNext.com forums)]]
	~~/w/images/e/e6/NEXT_GPIO_location.jpg\|J15 position on circuit board~~
	~~</gallery>~~