Expansion Bus Enable Register - Revision history

Ped7g: core 3.1.3 changes/refresh

2020-03-30T09:19:07Z

core 3.1.3 changes/refresh

← Older revision		Revision as of 10:19, 30 March 2020
Line 11:		Line 11:
	\|-		\|-
	\| 7 \|\| 1 to enable Expansion Bus		\| 7 \|\| 1 to enable Expansion Bus
			\|-
			\| 6 \|\| (since core 3.1.3) 1 to enable romcs rom replacement from divmmc banks 14/15
	\|-		\|-
	\| 5 \|\| 1 to disable I/O cycles and ignore IORQULA		\| 5 \|\| 1 to disable I/O cycles and ignore IORQULA
Line 19:		Line 21:
	\|-		\|-
	\| 3 \|\| 1 to enable Expansion Bus		\| 3 \|\| 1 to enable Expansion Bus
			\|-
			\| 2 \|\| (since core 3.1.3) 1 to enable romcs rom replacement from divmmc banks 14/15
	\|-		\|-
	\| 1 \|\| 1 to disable I/O cycles and ignore IORQULA		\| 1 \|\| 1 to disable I/O cycles and ignore IORQULA

Ped7g: core 3.0.5 changes/refresh

2019-12-04T22:58:56Z

core 3.0.5 changes/refresh

← Older revision		Revision as of 23:58, 4 December 2019
Line 3:		Line 3:
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Expansion bus ~~controls~~/config		\|ShortDesc=Expansion bus enable/config
	}}		}}
	~~Read (may change in the future):~~
	{\|class="wikitable"		{\|class="wikitable"
	! Bit !! Description		! Bit !! Description
	\|-		\|-
	\| 7 \|\| ~~ROMCS is being asserted on the expansion bus~~		\| \|\| Values affecting machine immediately
	\|-		\|-
	\| 6 \|\| Expansion ~~bus is currently enabled~~		\| 7 \|\| 1 to enable Expansion Bus
	\|-		\|-
	\| 5 \|\| ~~Max clock is always propagated~~ to ~~the expansion bus~~		\| 5 \|\| 1 to disable I/O cycles and ignore IORQULA
	\|-		\|-
	\| 4 \|\| ~~0 indicates the 48K rom is locked in place~~		\| 4 \|\| 1 to disable memory cycles and ignore ROMCS
	\|-		\|-
	\| ~~3-2~~ \|\| ~~Reserved~~		\| \|\| After soft reset (will be copied to bits 7-4)
	\|-		\|-
	\| ~~1-0~~ \|\| ~~Max cpu speed while the expansion bus is enabled~~		\| 3 \|\| 1 to enable Expansion Bus
	\|}

	~~Write (may change in the future):~~
	~~{\|class="wikitable"~~
	~~! Bit !! Description~~
	\|-
	~~\| 7 \|\| Make change immediate otherwise changes are noted for next soft reset~~
	\|-
	~~\| 6 \|\| Enable the expansion bus (hard reset = 0)~~
	\|-		\|-
	\| 5 \|\| ~~Always propagate the max clock~~ to ~~the expansion bus (hard reset = 0)~~		\| 1 \|\| 1 to disable I/O cycles and ignore IORQULA
	\|-		\|-
	\| ~~4 \|\| 0 to lock the 48k rom in place (hard reset =~~ 0)		\| 0 \|\| 1 to disable memory cycles and ignore ROMCS
	\|-
	~~\| 3-2 \|\| Reserved, must be 0~~
	\|-
	\| 1~~-0 \|\| CPU speed when the expansion bus is enabled (currently fixed at 00 = 3.5 MHz) (hard reset = 00)~~
	\|}		\|}

			Set to 0 upon hard reset.

			(new register since core 3.0.5)

	(note: Next registers with number higher than $7F are inaccessible from Copper code)		(note: Next registers with number higher than $7F are inaccessible from Copper code)

Ped7g: core 3.0.5 changes/refresh

2019-12-04T22:52:19Z

core 3.0.5 changes/refresh

← Older revision		Revision as of 23:52, 4 December 2019
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=$81		\|Number=$80
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes

Ped7g: core 3.0.5 changes/refresh

2019-12-04T22:50:35Z

core 3.0.5 changes/refresh

← Older revision		Revision as of 23:50, 4 December 2019
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=$80		\|Number=$81
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes

Ped7g: Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh

2019-12-04T22:48:14Z

Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh

← Older revision		Revision as of 23:48, 4 December 2019
(No difference)

Ped7g: core 3.0 changes/refresh

2019-11-12T08:25:23Z

core 3.0 changes/refresh

New page

{{NextRegister
|Number=$80
|Readable=Yes
|Writable=Yes
|ShortDesc=Expansion bus controls/config
}}
Read (may change in the future):
{|class="wikitable"
! Bit !! Description
|-
| 7 || ROMCS is being asserted on the expansion bus
|-
| 6 || Expansion bus is currently enabled
|-
| 5 || Max clock is always propagated to the expansion bus
|-
| 4 || 0 indicates the 48K rom is locked in place
|-
| 3-2 || Reserved
|-
| 1-0 || Max cpu speed while the expansion bus is enabled
|}

Write (may change in the future):
{|class="wikitable"
! Bit !! Description
|-
| 7 || Make change immediate otherwise changes are noted for next soft reset
|-
| 6 || Enable the expansion bus (hard reset = 0)
|-
| 5 || Always propagate the max clock to the expansion bus (hard reset = 0)
|-
| 4 || 0 to lock the 48k rom in place (hard reset = 0)
|-
| 3-2 || Reserved, must be 0
|-
| 1-0 || CPU speed when the expansion bus is enabled (currently fixed at 00 = 3.5 MHz) (hard reset = 00)
|}

(note: Next registers with number higher than $7F are inaccessible from Copper code)