Expansion Bus Control Register - Revision history

Sol HSA: updated to 78a6ee50

2024-11-03T11:45:43Z

updated to 78a6ee50

← Older revision		Revision as of 12:45, 3 November 2024
Line 9:		Line 9:
	\|-		\|-
	\| 7 \|\| 1 if ROMCS is being asserted on the expansion bus (Read only, write 0)		\| 7 \|\| 1 if ROMCS is being asserted on the expansion bus (Read only, write 0)
			\|-
			\| 6 \|\| 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive)
			\|-
			\| 5 \|\| 1 to disable expansion bus nmi debounce (opus discovery)
	\|-		\|-
	\| 4 \|\| 1 to propagate the max CPU clock at all times including when the expansion bus is off		\| 4 \|\| 1 to propagate the max CPU clock at all times including when the expansion bus is off

Ped7g: core 3.0.5 changes/refresh

2019-12-04T23:07:50Z

core 3.0.5 changes/refresh

← Older revision		Revision as of 00:07, 5 December 2019
Line 5:		Line 5:
	\|ShortDesc=Expansion bus controls		\|ShortDesc=Expansion bus controls
	}}		}}
	~~Read (may change in the future):~~
	{\|class="wikitable"		{\|class="wikitable"
	! Bit !! Description		! Bit !! Description
	\|-		\|-
	\| 7 \|\| ROMCS is being asserted on the expansion bus		\| 7 \|\| 1 if ROMCS is being asserted on the expansion bus (Read only, write 0)
	\|-		\|-
	\| 6 \|\| ~~Expansion~~ bus is ~~currently enabled~~		\| 4 \|\| 1 to propagate the max CPU clock at all times including when the expansion bus is off
	\|-		\|-
	~~\| 5 \|\| Max clock is always propagated to the expansion bus~~		\| 1-0 \|\| max CPU speed when the expansion bus is on (currently fixed at 00 = 3.5MHz)
	\|-
	~~\| 4 \|\| 0 indicates the 48K rom is locked in place~~
	\|-
	~~\| 3-2 \|\| Reserved~~
	\|-
	\| 1-0 \|\| ~~Max cpu~~ speed ~~while~~ the expansion bus is ~~enabled~~
	\|}		\|}

	~~Write (may change in the future):~~		Set to 0 upon hard reset.
	~~{\|class="wikitable"~~
	~~! Bit !! Description~~		(new register since core 3.0.5)
	\|-
	~~\| 7 \|\| Make change immediate otherwise changes are noted for next soft reset~~
	\|-
	~~\| 6 \|\| Enable the expansion bus (hard reset =~~ 0)
	\|-
	~~\| 5 \|\| Always propagate the max clock to the expansion bus (~~hard reset ~~= 0)~~
	\|-
	~~\| 4 \|\| 0 to lock the 48k rom in place~~ (~~hard reset = 0)~~
	\|-
	\| 3~~-2 \|\| Reserved, must be~~ 0
	\|-
	~~\| 1-0 \|\| CPU speed when the expansion bus is enabled (currently fixed at 00 = 3~~.5 ~~MHz~~) ~~(hard reset = 00)~~
	\|}

	(note: Next registers with number higher than $7F are inaccessible from Copper code)		(note: Next registers with number higher than $7F are inaccessible from Copper code)

Ped7g: core 3.0.5 changes/refresh

2019-12-04T22:53:00Z

core 3.0.5 changes/refresh

← Older revision		Revision as of 23:53, 4 December 2019
Line 1:		Line 1:
	~~#REDIRECT [[~~Expansion ~~Bus~~ Enable ~~Register]]~~		{{NextRegister
			\|Number=$81
			\|Readable=Yes
			\|Writable=Yes
			\|ShortDesc=Expansion bus controls
			}}
			Read (may change in the future):
			{\|class="wikitable"
			! Bit !! Description
			\|-
			\| 7 \|\| ROMCS is being asserted on the expansion bus
			\|-
			\| 6 \|\| Expansion bus is currently enabled
			\|-
			\| 5 \|\| Max clock is always propagated to the expansion bus
			\|-
			\| 4 \|\| 0 indicates the 48K rom is locked in place
			\|-
			\| 3-2 \|\| Reserved
			\|-
			\| 1-0 \|\| Max cpu speed while the expansion bus is enabled
			\|}

			Write (may change in the future):
			{\|class="wikitable"
			! Bit !! Description
			\|-
			\| 7 \|\| Make change immediate otherwise changes are noted for next soft reset
			\|-
			\| 6 \|\| Enable the expansion bus (hard reset = 0)
			\|-
			\| 5 \|\| Always propagate the max clock to the expansion bus (hard reset = 0)
			\|-
			\| 4 \|\| 0 to lock the 48k rom in place (hard reset = 0)
			\|-
			\| 3-2 \|\| Reserved, must be 0
			\|-
			\| 1-0 \|\| CPU speed when the expansion bus is enabled (currently fixed at 00 = 3.5 MHz) (hard reset = 00)
			\|}

			(note: Next registers with number higher than $7F are inaccessible from Copper code)

Ped7g: Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh

2019-12-04T22:48:14Z

Ped7g moved page Expansion Bus Control Register to Expansion Bus Enable Register: core 3.0.5 change/refresh

New page

#REDIRECT [[Expansion Bus Enable Register]]