CPU Speed Register - Revision history

Ped7g at 19:46, 20 September 2020

2020-09-20T19:46:04Z

← Older revision		Revision as of 20:46, 20 September 2020
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	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Sets CPU Speed, reads actual speed.		\|ShortDesc=Sets [[CPU Speed control\|CPU Speed]], reads actual speed.
	}}		}}
	Read:		Read:

2020-09-20T18:32:41Z

← Older revision		Revision as of 19:32, 20 September 2020
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	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Sets ~~accelerated clock speed~~, reads actual speed.		\|ShortDesc=Sets CPU Speed, reads actual speed.
	}}		}}
	Read:		Read:
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	The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.		The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.

	The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch (i.e. instruction like NOP will take 5T instead of regular 4T), there is some chance this may be improved in the future.		The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch and memory read (i.e. instruction like NOP will take 5T instead of regular 4T and DMA transfer configured to 2T+2T will take 3T+2T instead), there is some chance this may be improved in the future.

2020-09-20T18:29:04Z

Ped7g moved page Turbo Control Register to CPU Speed Register: syncing naming with latest nextreg.txt

← Older revision		Revision as of 19:29, 20 September 2020
(No difference)

2020-05-29T10:30:26Z

trying out less sparse wording

← Older revision		Revision as of 11:30, 29 May 2020
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	\| 7-2 \|\| Reserved, must be 0		\| 7-2 \|\| Reserved, must be 0
	\|-		\|-
	\| 1-0 \|\| Set CPU speed (soft reset ~~= %00~~)		\| 1-0 \|\| Set CPU speed (is set to %00 on soft reset)
	%00 = 3.5MHz		%00 = 3.5MHz
	%01 = 7MHz		%01 = 7MHz

2019-12-04T23:20:24Z

core 3.0.5 changes/refresh

← Older revision		Revision as of 00:20, 5 December 2019
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	%01 = 7MHz		%01 = 7MHz
	%10 = 14MHz		%10 = 14MHz
	%11 = 28MHz (~~reserved for future, currently gets dropped to %10 14MHz~~)		%11 = 28MHz (works since core 3.0)
	\|}		\|}

	The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4).		The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.

			The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch (i.e. instruction like NOP will take 5T instead of regular 4T), there is some chance this may be improved in the future.

2019-11-11T12:17:18Z

core 3.0 changes/refresh

@@ Line 5: / Line 5: @@
 |ShortDesc=Sets accelerated clock speed, reads actual speed.
 }}
-Bit 1-0 = turbo: %00 = 3.5MHz, %01 = 7MHz, %10 = 14MHz (%00 after PoR or Hard-reset).
+The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4).

2019-04-14T10:00:22Z

4 revisions imported

← Older revision		Revision as of 11:00, 14 April 2019
(No difference)

2018-12-23T01:49:03Z

← Older revision		Revision as of 02:49, 23 December 2018
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	Bit 1-0 = turbo: %00 = 3.5MHz, %01 = 7MHz, %10 = 14MHz (%00 after PoR or Hard-reset).		Bit 1-0 = turbo: %00 = 3.5MHz, %01 = 7MHz, %10 = 14MHz (%00 after PoR or Hard-reset).

			When 14MHz turbo is used, and [[Layer 2]] is enabled (bit 1 {{PortNo\|$123B}}), the 14MHz speed is used only when BORDER/VBLANK/HBLANK areas of screen image are generated, during PAPER (centre 256x192 pixel area of screen) the CPU speed is dropped down to 7MHz. With [[Layer 2]] disabled, 14MHz CPU speed is stable.

	Reads actual CPU speed.		Reads actual CPU speed.

2018-12-20T22:59:33Z

Core 2.00.22 changes.

← Older revision		Revision as of 23:59, 20 December 2018
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	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Sets accelerated clock speed.		\|ShortDesc=Sets accelerated clock speed, reads actual speed.
	}}		}}

			Bit 1-0 = turbo: %00 = 3.5MHz, %01 = 7MHz, %10 = 14MHz (%00 after PoR or Hard-reset).

			Reads actual CPU speed.

2017-08-15T00:30:07Z

← Older revision		Revision as of 01:30, 15 August 2017
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	{{NextRegister		{{NextRegister
	\|Number=7		\|Number=$07
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Sets accelerated clock speed.		\|ShortDesc=Sets accelerated clock speed.
	}}		}}