Anti-brick Register - Revision history

Sol HSA: updated to 78a6ee50

2024-11-03T11:19:23Z

updated to 78a6ee50

← Older revision		Revision as of 12:19, 3 November 2024
Line 9:		Line 9:
	! Bit !! Effect		! Bit !! Effect
	\|-		\|-
	\| 7-2 \|\| ~~Reserved~~		\| 7 \|\| Reserved
			\|-
			\| 6-2 \|\| Core ID
	\|-		\|-
	\| 1 \|\| Button DRIVE (DivMMC) is pressed		\| 1 \|\| Button DRIVE (DivMMC) is pressed
Line 24:		Line 26:
	\| 6-5 \|\| Reserved, must be 0		\| 6-5 \|\| Reserved, must be 0
	\|-		\|-
	\| 4-0 \|\| Core ID 0-31 (default is 2) (only in config mode)		\| 4-0 \|\| Core ID 0-31 (default is 2) (only in config mode) *
	\|}		\|}
			* A write of an out of range core id is ignored; this is the preferred way to determine max id

	Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.		Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.

2020-04-06T05:26:33Z

trying to "fix" the description to be more in sync with official manual and latest nextreg.txt (still feels incomplete)

← Older revision		Revision as of 06:26, 6 April 2020
Line 16:		Line 16:
	\|}		\|}

	'''Write''' bit mapped ~~(only in config mode)~~:		'''Write''' bit mapped:
	{\| class="wikitable"		{\| class="wikitable"
	! Bit !! Effect		! Bit !! Effect
	\|-		\|-
	\| 7 \|\| ~~If 1 start~~ selected core~~, if 0~~ FPGA ~~loads the fixed anti-brick core~~		\| 7 \|\| Start selected core (reboot FPGA)
	\|-		\|-
	\| 6-5 \|\| Reserved, must be 0		\| 6-5 \|\| Reserved, must be 0
	\|-		\|-
	\| 4-0 \|\| Core ID 0-31 (default is 2)		\| 4-0 \|\| Core ID 0-31 (default is 2) (only in config mode)
	\|}		\|}

	Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.		Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.

2019-11-11T12:58:58Z

core 3.0 changes/refresh

← Older revision		Revision as of 13:58, 11 November 2019
Line 9:		Line 9:
	! Bit !! Effect		! Bit !! Effect
	\|-		\|-
	\| 7-2 \|\| Reserved~~, 0~~		\| 7-2 \|\| Reserved
	\|-		\|-
	\| 1 \|\| DivMMC ~~button~~ pressed		\| 1 \|\| Button DRIVE (DivMMC) is pressed
	\|-		\|-
	\| 0 \|\| Multiface ~~button~~ pressed		\| 0 \|\| Button M1 (Multiface) is pressed
	\|}		\|}

2019-04-19T23:16:40Z

← Older revision		Revision as of 00:16, 20 April 2019
Line 5:		Line 5:
	\|ShortDesc=Used within the [[Anti-brick system]].		\|ShortDesc=Used within the [[Anti-brick system]].
	}}		}}

	'''Read''' bit mapped:		'''Read''' bit mapped:
	{\| class="wikitable"		{\| class="wikitable"

2019-04-14T09:59:50Z

5 revisions imported

← Older revision	Revision as of 10:59, 14 April 2019
(No difference)

2018-12-20T23:22:53Z

← Older revision		Revision as of 00:22, 21 December 2018
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=$0A		\|Number=$10
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
Line 6:		Line 6:
	}}		}}

	~~Bit~~ mapped:		'''Read''' bit mapped:
	{\| class="wikitable"		{\| class="wikitable"
	! Bit !! Effect		! Bit !! Effect
	\|-		\|-
	\| 7 ~~\|\| FPGA loads reflashable core (if 0, FPGA loads the fixed anti-brick core)~~		\| 7-2 \|\| Reserved, 0
	\|-
	~~\| 6~~-2 \|\| Reserved
	\|-		\|-
	\| 1 \|\| DivMMC button pressed		\| 1 \|\| DivMMC button pressed
	\|-		\|-
	\| 0 \|\| Multiface button pressed		\| 0 \|\| Multiface button pressed
			\|}

			'''Write''' bit mapped (only in config mode):
			{\| class="wikitable"
			! Bit !! Effect
			\|-
			\| 7 \|\| If 1 start selected core, if 0 FPGA loads the fixed anti-brick core
			\|-
			\| 6-5 \|\| Reserved, must be 0
			\|-
			\| 4-0 \|\| Core ID 0-31 (default is 2)
	\|}		\|}

	Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.		Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.

2017-08-18T23:38:51Z

2017-08-18T21:51:47Z

@@ Line 3: / Line 3: @@
 |Readable=Yes
 |Writable=Yes
-|ShortDesc=Controls state of the [[Anti-brick system]].
+|ShortDesc=Used within the [[Anti-brick system]].
 }}

2017-08-15T00:22:50Z

← Older revision		Revision as of 01:22, 15 August 2017
Line 1:		Line 1:
	{{NextRegister		{{NextRegister
	\|Number=10		\|Number=$10
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Controls state of the [[Anti-brick system]].		\|ShortDesc=Controls state of the [[Anti-brick system]].
	}}		}}

2017-08-14T19:08:24Z

Created page with "{{NextRegister |Number=10 |Readable=Yes |Writable=Yes |ShortDesc=Controls state of the Anti-brick system. }}"

New page

{{NextRegister
|Number=10
|Readable=Yes
|Writable=Yes
|ShortDesc=Controls state of the [[Anti-brick system]].
}}