SpecNext Wiki - User contributions [en-gb]

Mouse

2025-12-15T13:56:39Z

Sol HSA: Assembler use link added

The Spectrum Next has a PS/2 port for connecting a PS/2 keyboard or mouse (or both via a splitter).

'''WARNING: Do not plug in or remove PS/2 devices with the power on.'''

A USB mouse plugged in via a USB-to-PS/2 converter will only work if the mouse itself supports the PS/2 protocol.

=== PS/2 Port and modes of operation ===

The "ps2" setting in the /machines/next/config.ini file determines the PS/2 port mode:

'''PS2=0''' is KEYBOARD mode where a PS/2 keyboard is plugged into the Next, or with a splitter you can use both a mouse and a keyboard.

'''PS2=1''' is MOUSE mode where the mouse should be plugged in directly. Do not use a splitter in this mode as it can have funny effects.

You can set this on boot by holding down SPACE, then pressing "E" to edit, moving down to "PS2" with the down arrow, and changing from Keyboard to Mouse with the right arrow.

You can use the "ps2mode" dot command to see which mode is active. The best place to set the value is in the tbblue .ini file, but if you start in the wrong mode then on the Next (or a membrane) keyboard you can type ps2mode -m to select MOUSE or ps2mode -k to select KEYBOARD.

===Use from assembler===

The relevant ports for mouse use are documented here:
https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/ports.txt#L505

=== Driver ===
The NextZXOS distribution includes a mouse driver from version 1.95 onwards.

All you need is the file MOUSE.DRV in the NextZXOS folder. The mouse can then be used from BASIC with the new DRIVER command.

This mouse driver is driver number 126. There will be a supported list of driver codes and any that use streams (this does not) will need to be allocated one from 65-90/A-Z or the lower case range (or both) so this avoids that area.

The driver is stopped and started with the 'install' and 'uninstall' DOT commands in the BIN directory:

<pre>.install /nextzxos/mouse.drv
</pre>

=== Sample BASIC programs ===

There is a demo program called NXMOUSE.BAS that uses Sprite and Text features for you to play with (in the /demos/mouse folder). The NXMOUSET.BAS program uses some of the features of the sprite cursor and lets you play with acceleration settings in Timex HiRes mode.

They both use sprites from the BREAKOUT test but, you can change line 300 to load any set you wish. Note that if you
hold the 's' button and move it around at times the sprite cursor will seem to disappear - that is because you have reached the maximum 12 sprites per display line.

You could modify the code to remove the tail of previously used sprites if you want but, it is quite fun to play with.

=== Mouse Driver API ===

DRIVER supports the following parameters:

<pre>DRIVER 126,1 TO %b,x,y
</pre>

This will get the current location of the mouse on a 192 x 640 grid with 0,0 in the top left of the outer border where sprites can go. It uses the higher X number to allow use in Timex mode where there are twice as many horizontal pixels.

<pre>%b@111</pre> will be the three buttons bit activated in combination so 1,2,4 or 3,5,6,7 for combinations.
<pre>%b>>4</pre> will be the current value of the wheel mouse from 0 to 15.

<pre>DRIVER 126,2{,sprite{,pattern}}
</pre>

The optional sprite number 0-63 and pattern number 0-63 will default to 0. This will cause that sprite to always be displayed (anywhere that clipping is not in effect) at the current X,Y coordinate - over a Timex screen it will sit between two pixels of course.

<pre>DRIVER 126,3
</pre>
Will disable the sprite cursor.

<pre>DRIVER 126,4{,attribute}
</pre>
will display an attribute based character cursor using the ULA attributes - this will cope with some screen changes but, not scrolling so remember to disable it when changing the screen wholesale.

So using the new features of NextOS to include a binary number (@) in an integer statement (%)

<pre>DRIVER 126,4,%@11100111
</pre>
Will set a Bright, Flashing, Green and White cursor. The first two 1's are Bright and Flash the next two groups of three are the paper and ink:

<pre>FTGRBGRB</pre> - where T=Bright.

<pre>DRIVER 126,5</pre>

will remove the Attribute based cursor.

<pre>DRIVER 126,6,x_threshold
</pre>
Where x_threshold is forced to be in the range 0-255 by using LSB only:

* 0 Means always accelerate the X direction
* 255 Means never accelerate the X direction

By default x_threshold is set at 32 which will trigger more rapid movement if you move the mouse quickly. You can adjust to suit your own preference.

The Y does not have the option as 0-192 pixels probably would not benefit but, it is not ruled out and you have the source to hack...

---

Based on the distribution readme by Tim Gilberts.

===Wireless Mice===

Most ps/2 mice commonly seen today are wired. One model of wireless mouse known to work well with the Next is the '''Microsoft Cordless WheelMouse & Receiver, Serial & PS/2, C57-00001'''. Brand-new old stock units can often be obtained on eBay.

Circuit Diagrams

2025-10-07T14:57:18Z

Sol HSA: gallerize images

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

<gallery>
DaughterLocation.jpg|Daughter board location
Circuit_daughter_board.png|Daughter board
</gallery>

 

== J13 - Daughter board connector - Issue 4 ==

<gallery>
J13-I4-DaughterLocation.png|J13-I4 daughter location
J13-I4-CircuitDaughterBoard.png|J14-I4 circuit daughterboard
</gallery>

 

== J15 - Next GPIO - Issue 2A/2B ==

<gallery>
NEXT_GPIO_location.jpg|Next GPIO location
NEXT_GPIO.png|Next GPIO
</gallery>

 

== J15 - Next GPIO - Issue 4 ==

<gallery>
J15-I4-GPIOLocation.png|J15-I4 GPIO Location
J15-I4-CircuitGPIO.png|J16-I4 Circuit GPIO
</gallery>

 

== CN5 - Expansion bus (edge connector) ==

<gallery>
Expansion_bus_location.jpg|Expansion bus location
Expansion_bus.png|Expansion bus
</gallery>

 

== J10/J11 - Memory Expansion Ports ==

<gallery>
Mem_Expansion_location.jpg|Mem Expansion location
Mem_Expansion.png|Mem Expanstion
</gallery>

 

== J4/J7 J8/J14 - Joystick Ports ==

<gallery>
Joystick_Ports_Location.jpg|Joystick Ports Location
Joystick_Ports.png|Joystick Ports
</gallery>

 

== CN1 - VGA Video Port ==

<gallery>
Video_Port_Location.jpg|Video Port Location
Video_Port.png|Video Port
</gallery>

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

<gallery>
Digital Port Location.jpg|Digital Port Location
Next Digital Port.png|Next Digital Port
</gallery>

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

<gallery>
SD_Reader_Port_Location.jpg|SD reader port location
SD_Reader_Main.png|SD reader main
</gallery>

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

<gallery>
SD_Reader_Daughter_Port_Location.jpg|SD reader daughter port location
SD_Reader.png|SD reader
</gallery>

 

== Accelerator Board ==

<gallery>
Accelerator_Port_Location.jpg|Accelerator port location
Accelerator_Port.png|Accelerator port
</gallery>

 

== Real Time Clock (RTC) ==

<gallery>
RTC_Port_Location.jpg|RTC port location
RTC_Port.png|RTC port
</gallery>

 

== CN9 - ESP8266-01/RS-232 Port ==
<gallery>
Wifi_Port_Location.jpg|Wifi port location
Next_ESP_Port.png|Next ESP port
</gallery>

GPIO Socket (J15)

2025-10-07T14:47:53Z

Sol HSA: gallerize images

The GPIO socket, marked J15 on the circuit board, allows access to several different power and data lines:

* I2C serial protocol
* UART
* Spare pins on the [[FPGA]]
* 5v, 3.3v and GND

The UART is also used for the [[ESP8266-01|ESP Wi-fi module]], and can't be used from the GPIO without removing the ESP module. I2C is also used to communicate with the [[RTC|real time clock]] module.

The GPIO is not populated and requires a socket to be installed (2 x 10 IDC 2.54mm spc. Male Pin Header). Pull up/down resistors may be required for some pins to limit current.

<gallery>
NEXT GPIO location.jpg|J15 position on circuit board
NEXT_GPIO.png|GPIO pinout image
</gallery>

In June 2019 it was announced that pins 4 and 17 of J15 would be used for two additional keyboard connections on full cased Nexts. This is factory fitted on 2B boards with a two slot connector for the additional two lines on a third membrane tail. The extra data is handled by the VHDL in the FPGA so it still appears as a standard 48K Membrane but, without the complexity of three layers needed.

This change does mean it is slightly harder to use J15 as the socket overlaps some ajoining holes slightly.

RTC

2025-10-07T14:46:28Z

Sol HSA: gallerize images

A Real Time Clock (RTC) and Wi-Fi module were optional additions to the full cased Spectrum Next at the time of the original Kickstarter. They can be added to development boards and units that don't already have them, although the RTC requires soldering components to the board (whilst the Wi-Fi module is push-fit).

== Hardware Requirements ==

Adding a RTC requires the following components:

* 12pF Crystal
* DS1307 IC
* 8 pin DIL Socket
* CR2032 Holder
* CR2032 Battery

(6pF Crystals have been reported to work)

This is the mounting position on the PCB:

<gallery>
RTC_Port_Location.jpg|port location
RTC_Port.png|pinout
</gallery>

== Software Support ==

The [https://www.specnext.com/latestdistro/ TBBlue SD Distribution] contains dot commands "DATE" and "TIME" for working with the RTC:

{|
|-
| .DATE "31/12/2017" || Set the date to new years eve
|-
| .DATE || Print the current date
|-
| .TIME "00:30:00:" || Set the time to 30 minutes after midnight
|-
| .TIME || Print the current time
|-
| .TIME -h || Print help message
|}

You can also set the time with the .NXTP command if you have WIFI setup and configured.

If you use these without a RTC soldered to the board they will just give an error that no signature is found or No ACK received. You can however use the option TIME -d to get the contents of the chip which will be junk if the RTC is not fitted but, but may help to diagnose any problems getting it working.

When the RTC is fitted, as long as it has been set the date and time automatically appear in the NextZXOS menus. The ".ls" command will print a file listing with dates, and "cat exp" will show times as well.

You can get the contents of a dot command into a string using this NextBASIC:

DIM a$(100):OPEN #2,"v>a$":.TIME:CLOSE #2:PRINT a$

You can effectively "touch" a file in BASIC to update its timestamp with:

OPEN #4,"u>filename":CLOSE #4

The RTC is connected to the I2C bus. Also supplied is a DOT command called I2CSCAN - this will search the I2C bus for any devices found which can help in seeing what is connected. You should see at least one device at 0x68 if the RTC chip is connected. If you see others then they are likely parts of the HDMI connection or maybe you have something connected on J15.

Further information, including ESXDOS support, can be found on the TBBlue Distribution in the file \docs\extra-hw\rtc\RTCI2CTIMEDATEreadme.txt and \docs\nextzxos\NextZXOS_and_esxDOS_APIs.pdf

Extended Z80 instruction set

2025-10-07T14:39:23Z

Sol HSA: link fixes

This is a general list of Z80 and Z80N instructions with descriptions. The instructions specific to Z80N have the [[#Z80N_instructions_opcodes|encodings described first]].

For a table of summaries without additional descriptions see the [[Z80 Instruction Table]]. There's also an external [https://table.specnext.dev/ Z80N opcode value matrix on specnext.dev].

=== Z80N instructions opcodes ===

This is a table of the instructions and the encodings of all '''Next-specific''' Z80 instructions:

{| class="wikitable sortable"
|-
! Instruction !!data-sort-type="text"| Encoding (2-4 bytes) (hex) !! T-States !! Description !! 4 letter
|-
|<code> <code>SWAPNIB</code> </code>|| <code>ED 23</code> || 8 || Swap the nibbles (4-bits) of A || SWAP
|-
|<code> <code>MIRROR A</code> </code>|| <code>ED 24</code> || 8 || Mirror bits 0..7 to 7..0 of A || MIRR
|-
|<code> <code>TEST $im8</code> </code>|| <code>ED 27</code> value || 11 || Change flags as AND A but A stays unaffected ||style="color:DarkGrey;"| TEST
|-
|<code> <code>BSLA DE,B</code> </code>|| <code>ED 28</code> || 8 || Shift left DE for B bits ||style="color:DarkGrey;"| BSLA
|-
|<code> <code>BSRA DE,B</code> </code>|| <code>ED 29</code> || 8 || Shift right signed DE for B bits ||style="color:DarkGrey;"| BSRA
|-
|<code> <code>BSRL DE,B</code> </code>|| <code>ED 2A</code> || 8 || Shift right DE for B bits ||style="color:DarkGrey;"| BSRL
|-
|<code> <code>BSRF DE,B</code> </code>|| <code>ED 2B</code> || 8 || Shift right DE, filling 1 for B bits ||style="color:DarkGrey;"| BSRF
|-
|<code> <code>BRLC DE,B</code> </code>|| <code>ED 2C</code> || 8 || Rotate left DE for B bits ||style="color:DarkGrey;"| BRLC
|-
|<code> <code>MUL D,E</code> </code>|| <code>ED 30</code> || 8 || Multiply D with E, result in DE ||style="color:DarkGrey;"| MUL
|-
|<code> <code>ADD HL,A</code> </code>|| <code>ED 31</code> || 8 || Add unsigned A to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,A</code> </code>|| <code>ED 32</code> || 8 || Add unsigned A to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,A</code> </code>|| <code>ED 33</code> || 8 || Add unsigned A to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD HL,$im16</code> </code>|| <code>ED 34 low high</code> || 16 || Add a constant to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,$im16</code> </code>|| <code>ED 35 low high</code> || 16 || Add a constant to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,$im16</code> </code>|| <code>ED 36 low high</code> || 16 || Add a constant to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>PUSH $im16</code> </code>|| <code>ED 8A high low</code> || 23 || Push a constant ||style="color:DarkGrey;"| PUSH
|-
|<code> <code>OUTINB</code> </code>|| <code>ED 90</code> || 16 || OUTI, but don't change B || OTIB
|-
|<code> <code>NEXTREG $im8,$im8</code> </code>|| <code>ED 91 register value</code> || 20 || Write v to Next register r || NREG
|-
|<code> <code>NEXTREG $im8,A</code> </code>|| <code>ED 92 register</code> || 17 || Write A to Next register r || NREG
|-
|<code> <code>PIXELDN</code> </code>|| <code>ED 93</code> || 8 || HL as a pixel address moved one line down || PXDN
|-
|<code> <code>PIXELAD</code> </code>|| <code>ED 94</code> || 8 || HL := as ULA pixel address from D==Y E==X || PXAD
|-
|<code> <code>SETAE</code> </code>|| <code>ED 95</code> || 8 || Get A as a mask for ULA pixel from E || STAE
|-
|<code> <code>JP (C)</code> </code>|| <code>ED 98</code> || 13 || IN (C) then jump to a 64 byte section ||style="color:DarkGrey;"| JP
|-
|<code> <code>LDIX</code> </code>|| <code>ED A4</code> || 16 || Extended LDI byte copy ||style="color:DarkGrey;"| LDIX
|-
|<code> <code>LDWS</code> </code>|| <code>ED A5</code> || 14 || Byte copy as for Layer 2 ||style="color:DarkGrey;"| LDWS
|-
|<code> <code>LDDX</code> </code>|| <code>ED AC</code> || 16 || Extended LDD byte copy ||style="color:DarkGrey;"| LDDX
|-
|<code> <code>LDIRX</code> </code>|| <code>ED B4</code> || 21/16 || Extended LDIR || LIRX
|-
|<code> <code>LDPIRX</code> </code>|| <code>ED B7</code> || 21/16 || Byte copy as for a pattern fill || LPRX
|-
|<code> <code>LDDRX</code> </code>|| <code>ED BC</code> || 21/16 || Extended LDDR || LDRX
|}

More details and the explanations of all Z80 instructions implemented in the Next Z80 CPU follow.

Notes:

* The encoding of the operand of the <code>PUSH $im16</code> is unique: it is the only operand encoded as big-endian.
* The timings (T-States) are based on some limited testing and may not be accurate.
* The shorter aliases of the official mnemonics (the 4-letter column) are those suggested in an initiative led by Matt Davies, the author of Odin assembler, editor and debugger tool for ZX Next.
* A relevant early source for this table could be [https://github.com/z88dk/z88dk/issues/312#issuecomment-322659205 a Christmas 2018 edit of a comment in a discussion of an issue 312 of z88dk].

=== Notation ===
* In the descriptions ''any 8-bit register'' means A, B, C, D, E, H, and L. The registers named F, I and R aren't a part of this set even if they are technically 8 bit registers. Additionally, IXH, IXL, IYH, IYL, which are the high and low byte parts of IX and IY, can be used in some of the instructions as 8-bit registers although this wasn't documented for the original Z80.
* IXY means IX or IY.
* For the status field:
** S means Standard. It's in the Z80 manual. Everything should support it.
** U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
** E means Extension. It ''only'' works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
* Each of the flag effects is documented as follows:
** - means the flag is unchanged.
** 1 or 0 mean the flag is set or reset as appropriate.
** ? means we don't know what effect the instruction has on the flag.
** ! means the instruction has an unusual effect on the flag which is documented in the description.
** S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
** P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it checks BC as loop counter for some of the block copy and search instructions: P/V = (BC != 0)

=== Register and Data manipulation ===
;LD (LoaD)

{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LD r, r' </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||r := r'
|-
|<code>LD r,n </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||7 ||r := n
|-
|<code>LD r, (HL) </code>||Register ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||r := HL*
|-
|<code>LD r, (IXY+d) </code>||Register ||Indexed ||S ||- ||- ||- ||- ||- ||- ||19 ||r := (IXY+d)*
|-
|<code>LD (HL),r </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||7 ||HL* := r
|-
|<code>LD (IXY+d),r </code>||Indexed ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+D)* := r
|-
|<code>LD (HL), n </code>||Indirect ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||HL* := n
|-
|<code>LD (IXY+d), n </code>||Indexed ||Immediate ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+d)* := n
|-
|<code>LD A, (BC/DE) </code>||Accumulator ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||A := rr*
|-
|<code>LD A, (nn) </code>||Accumulator ||Address ||S ||- ||- ||- ||- ||- ||- ||13 ||A := (nn)*
|-
|<code>LD (BC/DE), A </code>||Indirect ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||7 ||rr* := A
|-
|<code>LD (nn), A </code>||Address ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||13 ||(nn)* := A
|-
|<code>LD A, I </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := I; P/V:=IFF2
|-
|<code>LD A, R </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := R; P/V:=IFF2
|-
|<code>LD I, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||I := A
|-
|<code>LD R, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||R := A
|-
|<code>LD BC/DE/HL/SP, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||rr := nn
|-
|<code>LD IXY, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||14 ||rr := nn
|-
|<code>LD HL, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||16 ||HL := (nn)*
|-
|<code>LD BC/DE/SP/IXY, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||20 ||rr := (nn)*
|-
|<code>LD (nn), HL </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||16 ||(nn)* := HL
|-
|<code>LD (nn), BC/DE/SP/IXY </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||20 ||(nn)* := rr
|-
|<code>LD SP, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||6 ||SP := HL
|-
|<code>LD SP, IXY </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||10 ||SP := IXY
|}
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
:* Any 8-bit register can be:
:** loaded with an immediate value;
:** loaded with the contents of any other 8-bit register except I and R;
:** loaded with the contents of, or stored in, memory pointed to by HL;
:** loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
:* Additionally, the accumulator A (only) can be:
:** loaded with the contents of, or stored in, memory pointed to by BC or DE;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address;
:** loaded with the contents of I or R.
:* Any 16-bit register pair can be:
:** loaded with an immediate value;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address.
:* Additionally, SP (only) can be:
:** loaded with the contents of HL, IX, or IY.
:** The planned '''ld hl, sp''' didn't make it to Next yet, one possible workaround is: '''ld hl,0'''; '''add hl,sp''';
:* Memory referred to by HL or through IX can be assigned immediate values.
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
:LD instructions do not alter any flags unless I or R are loaded into A.

;EX (EXchange)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EX DE, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(DE,HL)
|-
|<code>EX AF, AF' </code>||Register ||Register ||S ||! ||! ||! ||! ||! ||! ||4 ||swap(AF,AF')
|-
|<code>EX (SP), HL </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||swap(SP*,HL)
|-
|<code>EX (SP), IXY </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||23 ||swap(SP*,IXY)
|}
:Exchanges the contents of two sources. The only permitted combinations are
:* Exchanging DE and HL;
:* Exchanging AF and AF';
:* Exchanging HL, IX, or IY with the contents of memory pointed to by SP.

;EXX (EXchange all)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EXX </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(BC,BC');swap(DE,DE');swap(HL,HL')
|}
:Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.

;PUSH
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PUSH BC/DE/HL/AF </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||SP-=2; SP*:=rr
|-
|<code>PUSH IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||15 ||SP-=2; SP*:=rr
|-
|<code>PUSH nn </code>||Immediate ||- ||E ||- ||- ||- ||- ||- ||- ||23 ||SP-=2; SP*:=nn
|}
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.

;POP
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>POP BC/DE/HL </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr:=SP*; SP+=2
|-
|<code>POP AF </code>||Register ||- ||S ||! ||! ||! ||! ||! ||! ||10 ||rr:=SP*; SP+=2
|-
|<code>POP IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||rr:=SP*; SP+=2
|}
:Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.
:Popping into AF does set value of flag register F directly to low 8 bits of value from stack.

=== Block Copy ===
;LDI (LoaD and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDI </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE++; HL++; BC--
|}
:Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;LDIR (LoaD and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIR </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||21x+16 ||do LDI while(BC>0)
|}
:Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).
:Flag effects are the same as LDI except that P/V will always be reset, because BC by definition reaches 0 before this instruction ends (normally - unless something overwrites LDIR opcode while BC>0).
:Interrupts may interrupt LDIR instruction while looping (after each single LDI sub-part finished) and LDIR will resume after and finish loop properly.

;LDD (LoaD and Decrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDD </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE--; HL--; BC--
|}
:Same as LDI, but subtracts 1 from DE and HL instead of adding.

;LDDR (LoaD and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDDR </code>||- ||- ||S ||- ||0 ||0 ||0 ||- ||- ||21x+16 ||do LDD while(BC>0)
|}
:Same as LDIR but loops LDD instead of LDI.

;LDWS
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDWS </code>||- ||- ||E ||- ||0 ||! ||S ||S ||S ||14 ||DE*:=HL*; INC L; INC D;
|}
:Next-only extended opcode. Copies the byte pointed to by HL to the address pointed to by DE and increments only L and D. This is used for vertically copying bytes to the Layer 2 display.
:The flags are identical to what the '''INC D''' instruction would produce.
:Note the source data are read only from single 256B (aligned) block of memory, because only L is incremented, not HL.

;LDIX, LDIRX, LDDX, LDDRX
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL++; BC--
|-
|<code>LDIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDIX while(BC>0)
|-
|<code>LDDX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL--; BC--
|-
|<code>LDDRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDDX while(BC>0)
|}
:Next-only extended opcodes. Behave similarly as their non-X equivalents except the byte is not copied if it is equal to A and LDDX/LDDRX advance DE by incrementing it (like LDI), while HL is decremented (like LDD).
:Second difference to non-X instructions (as usual with next-only opcodes due to implementation), the extended ones don't modify any flags.

;LDPIRX
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDPIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
|}
:Similar to LDIRX except the source byte address is not just HL, but is obtained by using the top 13 bits of HL and the lower 3 bits of DE and HL does not increment during whole loop (HL works as base address of aligned 8 byte lookup table, DE works as destination and also wrapping index 0..7 into table). This is intended for "pattern fill" functionality.

=== Block Search ===
;CPI (ComPare and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPI </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL++; BC--
|}
:Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;CPIR (ComPare and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPIR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPI while (!Z && BC>0)
|}
:Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0).
:Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.

;CPD (ComPare and Decrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPD </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL--; BC--
|}
:Same as CPI, but subtracts 1 from HL instead of adding it.

;CPDR (ComPare and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPDR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPD while (!Z && BC>0)
|}
:Same as CPIR but loops CPD instead of CPI.

=== Arithmetic ===
;ADD
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADD A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r
|-
|<code>ADD A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n
|-
|<code>ADD A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*
|-
|<code>ADD A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*
|-
|<code>ADD HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||11 ||HL+=rr
|-
|<code>ADD IXY, BC/DE/IXY/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||15 ||IXY+=rr
|-
|<code>ADD HL/DE/BC, A </code>||Register ||Register ||E ||? ||- ||- ||- ||- ||- ||8 ||rr+=unsigned A
|-
|<code>ADD HL/DE/BC, nn </code>||Register ||Immediate ||E ||- ||- ||- ||- ||- ||- ||16 ||rr+=nn
|}
:Adds values together. Legal combinations are:
:* When adding 8-bit values the first parameter must be A and the second may be:
:** The contents of an 8-bit register;
:** An immediate value;
:** The contents of memory pointed to by HL or by indexing based on IX or IY.
:* When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register.
:* For 16 bit additions (regular Z80), H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)
:* On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A (A will be zero extended to 16 bits) or an 16bit immediate value.

;ADC (ADd with Carry)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADC A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r+(CF?1:0)
|-
|<code>ADC A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n+(CF?1:0)
|-
|<code>ADC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*+(CF?1:0)
|-
|<code>ADC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*+(CF?1:0)
|-
|<code>ADC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||V ||! ||S ||S ||15 ||HL+=rr+(CF?1:0)
|}
:Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if carry from bit 11; otherwise, it is reset.

;SUB
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SUB r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A -= r
|-
|<code>SUB n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= n
|-
|<code>SUB (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= HL*
|-
|<code>SUB (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A -= (IXY+d)*
|}
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.

;SBC (SuBtract with Carry, er, borrow)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SBC A, r </code>||Accumulator ||Register ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=(r+(CF?1:0))
|-
|<code>SBC A, n </code>||Accumulator ||Immediate ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(n+(CF?1:0))
|-
|<code>SBC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(HL*+(CF?1:0))
|-
|<code>SBC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=((IXY+d)+(CF?1:0))
|-
|<code>SBC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||1 ||V ||! ||S ||S ||15 ||HL-=(rr+(CF?1:0))
|}
:Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset.

;AND, OR, XOR
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>AND r </code>||Register ||- ||S ||0 ||0 ||P ||1 ||S ||S ||4 ||A := A & r
|-
|<code>AND n </code>||Immediate ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & n
|-
|<code>AND (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & HL*
|-
|<code>AND (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||1 ||S ||S ||19 ||A := A & (IXY+d)*
|-
|<code>OR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A OR r
|-
|<code>OR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR n
|-
|<code>OR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR HL*
|-
|<code>OR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A OR (IXY+d)*
|-
|<code>XOR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A ^ r
|-
|<code>XOR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ n
|-
|<code>XOR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ HL*
|-
|<code>XOR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A ^ (IXY+d)*
|}
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.

:XOR A is faster and shorter than LD A,0

;MIRROR
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MIRROR A </code>||Register ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A[76543210]:=A[01234567]
|}
:Next extended opcode. Mirrors (reverses the order) of bits in the accumulator. Older core versions supported MIRROR DE, but this was removed.

;CP (ComPare)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CP r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=r?
|-
|<code>CP n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=n?
|-
|<code>CP (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=HL*?
|-
|<code>CP (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=(IXY+d)?
|}
:Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
:* CP is ''not'' equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.

;TEST
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>TEST n </code>||Immediate ||- ||E ||S ||? ||P ||S ||S ||S ||11 ||A&n?
|}
: Next extended opcode. Similar to CP, but performs an AND instead of a subtraction.

;INC (INCrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INC r </code>||Register ||- ||S ||- ||0 ||! ||S ||S ||S ||4 ||r++
|-
|<code>INC (HL) </code>||Indirect ||- ||S ||- ||0 ||! ||S ||S ||S ||11 ||HL*++
|-
|<code>INC (IXY+d) </code>||Indexed ||- ||S ||- ||0 ||! ||S ||S ||S ||23 ||(IXY+d)*++
|-
|<code>INC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr++
|-
|<code>INC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr++
|}
:Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
:* INC A is faster than ADD 1.

;DEC (DECrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DEC r </code>||Register ||- ||S ||- ||1 ||! ||S ||S ||S ||4 ||r--
|-
|<code>DEC (HL) </code>||Indirect ||- ||S ||- ||1 ||! ||S ||S ||S ||11 ||HL*--
|-
|<code>DEC (IXY+d) </code>||Indexed ||- ||S ||- ||1 ||! ||S ||S ||S ||23 ||(IXY+D)*--
|-
|<code>DEC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr--
|-
|<code>DEC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr--
|}
:Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
:* DEC A is faster than SUB 1.

;RLC (Rotate Left Circular)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=x; CF:=x
|-
|<code>RLC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=x; CF:=x
|-
|<code>RLC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=x; CF:=x
|-
|<code>RLC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=x; CF:=x; r:=(IX+d)*
|}
:Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.

;RL (Rotate Left)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x
|-
|<code>RL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=CF; CF:=x
|-
|<code>RL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=CF; CF:=x
|-
|<code>RL r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=CF; CF:=x; r:=(IX+d)*
|}
:Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.

;RRC, RR (Rotate Right Circular, Rotate Right)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=x; CF:=x
|-
|<code>RRC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=x; CF:=x
|-
|<code>RRC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=x; CF:=x
|-
|<code>RRC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=x; CF:=x; r:=(IX+d)*
|-
|<code>RR r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x
|-
|<code>RR (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=CF; CF:=x
|-
|<code>RR (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=CF; CF:=x
|-
|<code>RR r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=CF; CF:=x; r=(IX+d)*
|}
:Same as RLC and RL except they rotate right instead of left.

;SLA (Shift Left Arithmetic)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SLA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r<<1
|-
|<code>SLA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*<<1
|-
|<code>SLA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*<<1
|-
|<code>SLA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*<<1; r=(IX+d)*
|}
:Same as RL except bit 0 is set to zero, not the previous contents of Carry.

;SRA (Shift Right Arithmetic)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r>>1 OR r[7]
|-
|<code>SRA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*>>1 OR HL*[7]
|-
|<code>SRA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*>>1 OR (IXY+d)*[7]
|-
|<code>SRA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*>>1 OR (IX+d)*[7]; r:=(IX+d)*
|}
:Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry.

;SRL (Shift Right Logical)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||0 ||8 ||r:=unsigned(r)>>1
|-
|<code>SRL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||0 ||15 ||HL*:=unsigned(HL*)>>1
|-
|<code>SRL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1
|-
|<code>SRL r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1; r:=(IXY+d)*
|}
:Same as SLA except it shifts right instead of left.

;RLCA, RLA, RRCA, RRA
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=x; CF:=x
|-
|<code>RLA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x
|-
|<code>RRCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=x; CF:=x
|-
|<code>RRA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x
|}
:Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.

;SLL (Shift Left Logical)
:This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.

;SL1 or SLI (Shift Left and Add 1) or (Shift Left and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SL1 r </code>||Register ||- ||U ||! ||0 ||P ||0 ||S ||S ||8 ||r:=(r<<1)+1
|-
|<code>SL1 (HL) </code>||Indirect ||- ||U ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=(HL*<<1)+1
|-
|<code>SL1 (IXY+d) </code>||Indexed ||- ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1
|-
|<code>SL1 r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1; r=(IXY+d)*
|}
:Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.

;RLD (Rotate Left bcd Digit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]
|}
:Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.

;RRD (Rotate Right bcd Digit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]
|}
:Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.

;Barrel (variable amount) shift and rotate (cores v2+ only)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BSLA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&31) ||8
|-
|<code>BSRA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=signed(DE)>>(B&31) ||8
|-
|<code>BSRL DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=unsigned(DE)>>(B&31) ||8
|-
|<code>BSRF DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=~(unsigned(~DE)>>(B&31)) ||8
|-
|<code>BRLC DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&15) OR DE>>(16-B&15) ||8
|}
:Shift instructions use only bits 4..0 of B, BSLA shifts DE left, BSRA/BSRL/BSRF shifts DE right in arithmetic/logical/fill-one way. BRLC rotates DE left by B places, uses only bits 3..0 of B (to rotate right, use B=16-places).

If you are implementing BSRF in C (or similar), be careful with implicit variable type promotion. You will need to do something like this: DE:=~((uint16_t)~DE>>(B&31))

;CPL (ComPLement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPL </code>||- ||- ||S ||- ||1 ||- ||1 ||- ||- ||4 ||A:=~A
|}
:Inverts the contents of the accumulator.

;NEG (NEGate)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEG </code>||- ||- ||S ||! ||1 ||! ||S ||S ||S ||8 ||A:=0-A
|}
:Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.

;CCF (Complement Carry Flag)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CCF </code>||- ||- ||S ||! ||0 ||- ||! ||- ||- ||4 ||CF:=!CF
|}
:Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.

;SCF (Set Carry Flag)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SCF </code>||- ||- ||S ||1 ||0 ||- ||0 ||- ||- ||4 ||CF:=1
|}
:Sets the carry flag.

;BIT (test BIT)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BIT b,r </code>||Immediate ||Register ||S ||- ||0 ||? ||1 ||! ||? ||8 ||r[b]==1?
|-
|<code>BIT b,(HL) </code>||Immediate ||Indirect ||S ||- ||0 ||? ||1 ||! ||? ||12 ||HL*[b]==1?
|-
|<code>BIT b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||0 ||? ||1 ||! ||? ||20 ||(IXY+d)*[b]==1?
|}
:Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.

;SET (SET bit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SET b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r OR (1<<b)
|-
|<code>SET b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* OR (1<<b)
|-
|<code>SET b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* OR (1<<b)
|-
|<code>SET r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* OR (1<<b); r:=(IX+d)*
|-
|<code>SETAE </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=unsigned($80)>>(E&7)
|}
:Sets the numbered bit on target value. The possible targets are the same as BIT. The three parameter variant is undocumented and stores the result in a register as well as performing the SET.
:SETAE is a Next extended opcode which takes the bit number to set from E (only the low 3 bits) and sets whole A to value of that bit, but counted from top to bottom (E=0 will produce A:=$80, E=7 will produce A:=$01). This works as pixel mask for ULA bitmap modes, when E is 0..255 x-coordinate.

;RES (RESet bit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RES b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r & (~(1<<b))
|-
|<code>RES b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* & (~(1<<b))
|-
|<code>RES b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* & (~(1<<b))
|-
|<code>RES r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* & (~(1<<b)); r:=(IX+d)*
|}
:Resets the numbered bit on target value. The possible targets are the same as BIT.

;DAA (Decimal Adjust Accumulator)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DAA </code>||- ||- ||S ||! ||- ||P ||! ||S ||S ||8 ||if(A&$0F>$09 or HF) A±=$06; if(A&$F0>$90 or CF) A±=$60 (± depends on NF)
|}
:Modifies the contents of the accumulator based on the flags left by previous operation to correct for binary coded decimal (BCD).

;MUL (MULtiply)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MUL d,e </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||DE:=D*E
|}
:Next extended opcode. Multiplies D by E, storing 16 bit result into DE. Does not alter any flags (the opcode is not compatible with any of the R800/Z180/eZ80/... variants of MUL, it is solely Next specific).

;SWAPNIB (SWAP NIBbles)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SWAPNIB </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=A[3210]<<4 OR A[7654]>>4
|}
:Next extended opcode. Swaps the high and low nibbles of the accumulator.

;PIXELAD (PIXEL ADdress)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELAD </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
|}
:Next extended opcode. Takes E and D as the X,Y coordinate of a point and calculates the address of the byte containing this pixel in the pixel area of standard ULA screen 0, storing it in HL.

;PIXELDN (PIXEL DowN)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELDN </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||if(HL&$0700!=$0700) HL+=256; 
else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; 
else HL:=HL&$F81F+$0800
|}
:Updates the address in HL to move down by one line of pixels.

=== Control Flow ===
;JP (JumP)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=nn
|-
|<code>JP (HL) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC:=HL (not PC:=HL*)
|-
|<code>JP (IXY) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||PC:=IXY (not PC:=IXY*)
|-
|<code>JP (C) </code>||Register ||- ||E ||? ||? ||? ||? ||? ||? ||13 ||PC:=PC&$C000+IN(C)<<6
|}
:Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs ''look'' like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to. The JP (C) sets bottom 14 bits of current PC* to value read from I/O port: PC[13:0] = (IN (C) << 6) (can be used to execute code block read from a disk stream) * "current PC" is address of next instruction after JP (C), as the PC is advanced by fetching op code from memory and is already advanced when execution happens - if the JP instruction resides at the very end of 16k memory block (..FE or ..FF address), then newly composed PC value will land into following 16k block.

;JP cc (JumP conditionally)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP Z/NZ/NC/C/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||if cc PC:=nn
|}
:Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.

;JR (Jump Relative)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JR nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ||PC+=nn
|-
|<code>JR C/NC/Z/NZ, nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ; 7 if not cc ||if cc PC+=nn
|}
:Jumps to an alternate address by ''adding'' the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.

;DJNZ (Decrement reg. b and Jump if Not Zero)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DJNZ n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||13 ||B--; if B!=0 PC+=nn
|}
:Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.

;CALL
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CALL nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ||SP-=2; SP*:=PC; PC:=nn
|-
|<code>CALL Z/NZ/C/NC/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ; 10 if not cc ||if cc {SP-=2; SP*:=PC; PC:=nn}
|}
:Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.
:* If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)

;RET (RETurn)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RET </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=SP*; SP+=2
|-
|<code>RET Z/NZ/C/NC/PO/PE/P/M </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||11 ; 5 if not cc ||if cc {PC:=SP*; SP+=2}
|}
:POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.

;RETI (RETurn from Interrupt)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||PC:=SP*; SP+=2
|}
:Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).

;RETN (RETurn from Non-maskable interrupt)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETN </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||IFF1:=IFF2; PC:=SP*; SP+=2
|}
:Returns from a non-maskable interrupt service routine.

;RST (ReSTart)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RST n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||CALL n
|}
:Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.

;NOP (No OPeration)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NOP </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC+=1
|}
:Does "nothing" (just usual housekeeping like refreshing memory and advancing program counter to next instruction).

;HALT
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>HALT </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||waits for interrupt
|}
:Suspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.

;DI (Disable Interrupts)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=0; IFF2:=0
|}
:Disables maskable interrupts.

;EI (Enable Interrupts)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=1; IFF2:=1
|}
:Enables maskable interrupts (after next instruction, i.e. for example "EI RET" - the interrupt may happen only after RET instruction is finished (or "EI DI" pair of instructions will not allow any maskable interrupt to happen).

;IM (Interrupt Mode)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IM n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||Interrupt mode:=n
|}
:Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)

=== Input and Output ===
;IN r, (c); OUT (c), r
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN r, (c) </code>||Register ||Register ||S ||- ||0 ||P ||0 ||S ||S ||12 ||r := in(BC)
|-
|<code>OUT (c),r </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||12 ||out(BC,r)
|}
:Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.

;IN (c); OUT (c), 0
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN (c) </code>||Register ||- ||U ||- ||0 ||P ||0 ||S ||S ||12 ||in(BC)?
|-
|<code>OUT (c),0 </code>||Register ||Immediate ||U ||- ||- ||- ||- ||- ||- ||12 ||out(BC,0)
|}
:Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode. The Next FPGA does output zero, but some Z80 chips manufactured differently from early batches output different value like 255, so it is not recommended to use OUT (C),0 if you want to reuse your code also on classic ZX Spectrum or publish it as example.

;IN a, (n); OUT (n), a
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN A, (n) </code>||Accumulator ||Immediate ||S ||- ||- ||- ||- ||- ||- ||11 ||A := in(An)
|-
|<code>OUT (n),A </code>||Immediate ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||11 ||out(An,A)
|}
:Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.

;INI (INput and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL++; B--
|}
:Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.

;INIR (INput and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do INI while(B>0)
|}
:Loops INIR until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

;IND, INDR (INput and Decrement, INput and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IND </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL--; B--
|-
|<code>INDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do IND while(B>0)
|}
:Behave like INI and INIR except that HL is decremented instead of incremented.

;OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL++
|-
|<code>OTIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTI while (B>0)
|-
|<code>OUTD </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL--
|-
|<code>OTDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTD while (B>0)
|}
:Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented '''before''' the output instead of after. Condition check on B is performed '''after''', so that if OTIR starts with B=0 it loops 256 times.

;OUTINB (Out and Increment with No B)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTINB </code>||- ||- ||E ||? ||? ||? ||? ||? ||? ||16 ||out(BC,HL*); HL++
|}
:Next extended opcode. Behaves like OUTI, but doesn't decrement B.

;NEXTREG
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEXTREG n,n' </code>||Immediate ||Immediate ||E ||- ||- ||- ||- ||- ||- ||20 ||HwNextReg_n:=n'
|-
|<code>NEXTREG n, A </code>||Immediate ||Accumulator ||E ||- ||- ||- ||- ||- ||- ||17 ||HwNextReg_n:=A
|}
:Next extended opcode. Directly sets the [[Board feature control|Next Feature Control Registers]] without going through ports [[TBBlue_Register_Select]] and [[TBBlue Register Access]].

=== A note on some Z80-N specific observations ===
2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.

2025-01-25: Testing 3.02.x 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

=== Errata ===

This section lists the changes of the specification of the behavior of Z80N instructions, compared to the previous content of this wiki page.

2022-01-11: The previous versions of this page didn't match what was [http://www.z80.info/zip/z80-documented.pdf documented] for several years, that regular Z80 INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR instructions do modify carry flag (contrary to the official Z80 documentation and many Internet resources describing Z80 instructions).

Emulators

2025-10-07T14:34:30Z

Sol HSA: linkify known bugs

===== WARNING: =====

The current Next emulators are work-in-progress, missing several features of real HW Next, and emulating other features in less than cycle-accurate way (which become a "norm" for classic ZX Spectrum after two decades of emulators development). The differences in results between real Next and CSpect or ZEsarUX are to be expected - as a developer test your SW also with real HW to find any problems early. It may also help to read the known-bugs pages to have some rough idea what works and how accurately. There're also multiple test-suites and free games and demos which you can try to go through and compare the emulator output with real machine, to get familiar with the differences and adjust your workflow and expectations.
 

Also make sure to explore the command line options and configuration of each emulator, as there are multiple ways how to run them with different fidelity of emulation. When in doubt, you are welcome to join the official ZX Spectrum Next discord chat and ask for help at #emulator-help channel.
 

Currently the most UI and performance friendly emulator seems to be #CSpect, the most features/accurate emulation of core3.1.5 (but far from perfect) has ZESERUse (fork of ZEsarUX).

{| class="wikitable"
!Name||Author||Url||Known bugs||Description||OS||Source
|-
|CSpect||Mike Dailly||https://mdf200.itch.io/cspect||[[CSpect:known bugs]]||Emulates many features of the Next and includes a fully featured debugger, complete with 24bit breakpoints and an assembler||Windows(mac/linux mostlyworks through mono)||N
|-
|ZEsarUX||César Hernández Bañó||https://github.com/chernandezba/zesarux/releases Source: https://github.com/chernandezba/zesarux||[[ZEsarUX:known bugs]]||A full feature emulator including a debugger - sometimes updated to support Next (TBBlue)||Any||Y
|-
|ZESERUse||César Hernández Bañó + Peter Helcmanovsky||Source: https://github.com/ped7g/zesarux/tree/tbblue_small_fixes2||[[ZESERUse:known bugs]]||Currently most complete core3.1.5 emulation based on ZEsarUX 8.2 version (for windows executable check official Next discord or build it yourself - make sure you are building the "tbblue_small_fixes2" branch).||Any||Y
|-
|ZENext||César Hernández Bañó + Garry Lancaster||https://gitlab.com/garrylancaster/zenext|| |||ZX Next-only fork of ZEsarUX emulating most of the core 3.1.10 features to make it run NextZXOS 2.07 (missing some features like CTC timers).||Any||Y
|-
|Zeus||Design Design||http://www.desdes.com/products/oldfiles/zeus.htm|| || A PC cross-assembler which includes a Z80 emulator, which can emulate the ZX Spectrum 48K/128K hardware.||Windows||N
|}

Emulators

2025-10-07T14:30:23Z

Sol HSA: remove emulatorlisttop

===== WARNING: =====

The current Next emulators are work-in-progress, missing several features of real HW Next, and emulating other features in less than cycle-accurate way (which become a "norm" for classic ZX Spectrum after two decades of emulators development). The differences in results between real Next and CSpect or ZEsarUX are to be expected - as a developer test your SW also with real HW to find any problems early. It may also help to read the known-bugs pages to have some rough idea what works and how accurately. There're also multiple test-suites and free games and demos which you can try to go through and compare the emulator output with real machine, to get familiar with the differences and adjust your workflow and expectations.
 

Also make sure to explore the command line options and configuration of each emulator, as there are multiple ways how to run them with different fidelity of emulation. When in doubt, you are welcome to join the official ZX Spectrum Next discord chat and ask for help at #emulator-help channel.
 

Currently the most UI and performance friendly emulator seems to be #CSpect, the most features/accurate emulation of core3.1.5 (but far from perfect) has ZESERUse (fork of ZEsarUX).

{| class="wikitable"
!Name||Author||Url||Known bugs||Description||OS||Source
|-
|CSpect||Mike Dailly||https://mdf200.itch.io/cspect||CSpect:known bugs||Emulates many features of the Next and includes a fully featured debugger, complete with 24bit breakpoints and an assembler||Windows(mac/linux mostlyworks through mono)||N
|-
|ZEsarUX||César Hernández Bañó||https://github.com/chernandezba/zesarux/releases Source: https://github.com/chernandezba/zesarux||ZEsarUX:known bugs||A full feature emulator including a debugger - sometimes updated to support Next (TBBlue)||Any||Y
|-
|ZESERUse||César Hernández Bañó + Peter Helcmanovsky||Source: https://github.com/ped7g/zesarux/tree/tbblue_small_fixes2||ZESERUse:known bugs||Currently most complete core3.1.5 emulation based on ZEsarUX 8.2 version (for windows executable check official Next discord or build it yourself - make sure you are building the "tbblue_small_fixes2" branch).||Any||Y
|-
|ZENext||César Hernández Bañó + Garry Lancaster||https://gitlab.com/garrylancaster/zenext|| |||ZX Next-only fork of ZEsarUX emulating most of the core 3.1.10 features to make it run NextZXOS 2.07 (missing some features like CTC timers).||Any||Y
|-
|Zeus||Design Design||http://www.desdes.com/products/oldfiles/zeus.htm|| || A PC cross-assembler which includes a Z80 emulator, which can emulate the ZX Spectrum 48K/128K hardware.||Windows||N
|}

Emulators

2025-10-07T14:28:56Z

Sol HSA: couple empty cells

{{EmulatorListTop}}

===== WARNING: =====

The current Next emulators are work-in-progress, missing several features of real HW Next, and emulating other features in less than cycle-accurate way (which become a "norm" for classic ZX Spectrum after two decades of emulators development). The differences in results between real Next and CSpect or ZEsarUX are to be expected - as a developer test your SW also with real HW to find any problems early. It may also help to read the known-bugs pages to have some rough idea what works and how accurately. There're also multiple test-suites and free games and demos which you can try to go through and compare the emulator output with real machine, to get familiar with the differences and adjust your workflow and expectations.
 

Also make sure to explore the command line options and configuration of each emulator, as there are multiple ways how to run them with different fidelity of emulation. When in doubt, you are welcome to join the official ZX Spectrum Next discord chat and ask for help at #emulator-help channel.
 

Currently the most UI and performance friendly emulator seems to be #CSpect, the most features/accurate emulation of core3.1.5 (but far from perfect) has ZESERUse (fork of ZEsarUX).

{| class="wikitable"
!Name||Author||Url||Known bugs||Description||OS||Source
|-
|CSpect||Mike Dailly||https://mdf200.itch.io/cspect||CSpect:known bugs||Emulates many features of the Next and includes a fully featured debugger, complete with 24bit breakpoints and an assembler||Windows(mac/linux mostlyworks through mono)||N
|-
|ZEsarUX||César Hernández Bañó||https://github.com/chernandezba/zesarux/releases Source: https://github.com/chernandezba/zesarux||ZEsarUX:known bugs||A full feature emulator including a debugger - sometimes updated to support Next (TBBlue)||Any||Y
|-
|ZESERUse||César Hernández Bañó + Peter Helcmanovsky||Source: https://github.com/ped7g/zesarux/tree/tbblue_small_fixes2||ZESERUse:known bugs||Currently most complete core3.1.5 emulation based on ZEsarUX 8.2 version (for windows executable check official Next discord or build it yourself - make sure you are building the "tbblue_small_fixes2" branch).||Any||Y
|-
|ZENext||César Hernández Bañó + Garry Lancaster||https://gitlab.com/garrylancaster/zenext|| |||ZX Next-only fork of ZEsarUX emulating most of the core 3.1.10 features to make it run NextZXOS 2.07 (missing some features like CTC timers).||Any||Y
|-
|Zeus||Design Design||http://www.desdes.com/products/oldfiles/zeus.htm|| || A PC cross-assembler which includes a Z80 emulator, which can emulate the ZX Spectrum 48K/128K hardware.||Windows||N
|}

Emulators

2025-10-07T12:53:25Z

Sol HSA: rebuilt tables

{{EmulatorListTop}}

===== WARNING: =====

The current Next emulators are work-in-progress, missing several features of real HW Next, and emulating other features in less than cycle-accurate way (which become a "norm" for classic ZX Spectrum after two decades of emulators development). The differences in results between real Next and CSpect or ZEsarUX are to be expected - as a developer test your SW also with real HW to find any problems early. It may also help to read the known-bugs pages to have some rough idea what works and how accurately. There're also multiple test-suites and free games and demos which you can try to go through and compare the emulator output with real machine, to get familiar with the differences and adjust your workflow and expectations.
 

Also make sure to explore the command line options and configuration of each emulator, as there are multiple ways how to run them with different fidelity of emulation. When in doubt, you are welcome to join the official ZX Spectrum Next discord chat and ask for help at #emulator-help channel.
 

Currently the most UI and performance friendly emulator seems to be #CSpect, the most features/accurate emulation of core3.1.5 (but far from perfect) has ZESERUse (fork of ZEsarUX).

{| class="wikitable"
!Name||Author||Url||Known bugs||Description||OS||Source
|-
|CSpect||Mike Dailly||https://mdf200.itch.io/cspect||CSpect:known bugs||Emulates many features of the Next and includes a fully featured debugger, complete with 24bit breakpoints and an assembler||Windows(mac/linux mostlyworks through mono)||N
|-
|ZEsarUX||César Hernández Bañó||https://github.com/chernandezba/zesarux/releases Source: https://github.com/chernandezba/zesarux||ZEsarUX:known bugs||A full feature emulator including a debugger - sometimes updated to support Next (TBBlue)||Any||Y
|-
|ZESERUse||César Hernández Bañó + Peter Helcmanovsky||Source: https://github.com/ped7g/zesarux/tree/tbblue_small_fixes2||ZESERUse:known bugs||Currently most complete core3.1.5 emulation based on ZEsarUX 8.2 version (for windows executable check official Next discord or build it yourself - make sure you are building the "tbblue_small_fixes2" branch).||Any||Y
|-
|ZENext||César Hernández Bañó + Garry Lancaster||https://gitlab.com/garrylancaster/zenext||ZX Next-only fork of ZEsarUX emulating most of the core 3.1.10 features to make it run NextZXOS 2.07 (missing some features like CTC timers).||Any||Y
|-
|Zeus||Design Design||http://www.desdes.com/products/oldfiles/zeus.htm||A PC cross-assembler which includes a Z80 emulator, which can emulate the ZX Spectrum 48K/128K hardware.||Windows||N
|}

Extended Z80 instruction set

2025-10-07T12:18:11Z

Sol HSA: remove one }}

This is a general list of Z80 and Z80N instructions with descriptions. The instructions specific to Z80N have the [[#Z80N_instructions_opcodes|encodings described first]].

For a table of summaries without additional descriptions see the [[Z80 Instruction Table]]. There's also a [[Special:RunQuery/OpcodeQuery|special search for opcodes in the same table]] and an external [https://table.specnext.dev/ Z80N opcode value matrix on specnext.dev].

=== Z80N instructions opcodes ===

This is a table of the instructions and the encodings of all '''Next-specific''' Z80 instructions:

{| class="wikitable sortable"
|-
! Instruction !!data-sort-type="text"| Encoding (2-4 bytes) (hex) !! T-States !! Description !! 4 letter
|-
|<code> <code>SWAPNIB</code> </code>|| <code>ED 23</code> || 8 || Swap the nibbles (4-bits) of A || SWAP
|-
|<code> <code>MIRROR A</code> </code>|| <code>ED 24</code> || 8 || Mirror bits 0..7 to 7..0 of A || MIRR
|-
|<code> <code>TEST $im8</code> </code>|| <code>ED 27</code> value || 11 || Change flags as AND A but A stays unaffected ||style="color:DarkGrey;"| TEST
|-
|<code> <code>BSLA DE,B</code> </code>|| <code>ED 28</code> || 8 || Shift left DE for B bits ||style="color:DarkGrey;"| BSLA
|-
|<code> <code>BSRA DE,B</code> </code>|| <code>ED 29</code> || 8 || Shift right signed DE for B bits ||style="color:DarkGrey;"| BSRA
|-
|<code> <code>BSRL DE,B</code> </code>|| <code>ED 2A</code> || 8 || Shift right DE for B bits ||style="color:DarkGrey;"| BSRL
|-
|<code> <code>BSRF DE,B</code> </code>|| <code>ED 2B</code> || 8 || Shift right DE, filling 1 for B bits ||style="color:DarkGrey;"| BSRF
|-
|<code> <code>BRLC DE,B</code> </code>|| <code>ED 2C</code> || 8 || Rotate left DE for B bits ||style="color:DarkGrey;"| BRLC
|-
|<code> <code>MUL D,E</code> </code>|| <code>ED 30</code> || 8 || Multiply D with E, result in DE ||style="color:DarkGrey;"| MUL
|-
|<code> <code>ADD HL,A</code> </code>|| <code>ED 31</code> || 8 || Add unsigned A to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,A</code> </code>|| <code>ED 32</code> || 8 || Add unsigned A to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,A</code> </code>|| <code>ED 33</code> || 8 || Add unsigned A to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD HL,$im16</code> </code>|| <code>ED 34 low high</code> || 16 || Add a constant to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,$im16</code> </code>|| <code>ED 35 low high</code> || 16 || Add a constant to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,$im16</code> </code>|| <code>ED 36 low high</code> || 16 || Add a constant to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>PUSH $im16</code> </code>|| <code>ED 8A high low</code> || 23 || Push a constant ||style="color:DarkGrey;"| PUSH
|-
|<code> <code>OUTINB</code> </code>|| <code>ED 90</code> || 16 || OUTI, but don't change B || OTIB
|-
|<code> <code>NEXTREG $im8,$im8</code> </code>|| <code>ED 91 register value</code> || 20 || Write v to Next register r || NREG
|-
|<code> <code>NEXTREG $im8,A</code> </code>|| <code>ED 92 register</code> || 17 || Write A to Next register r || NREG
|-
|<code> <code>PIXELDN</code> </code>|| <code>ED 93</code> || 8 || HL as a pixel address moved one line down || PXDN
|-
|<code> <code>PIXELAD</code> </code>|| <code>ED 94</code> || 8 || HL := as ULA pixel address from D==Y E==X || PXAD
|-
|<code> <code>SETAE</code> </code>|| <code>ED 95</code> || 8 || Get A as a mask for ULA pixel from E || STAE
|-
|<code> <code>JP (C)</code> </code>|| <code>ED 98</code> || 13 || IN (C) then jump to a 64 byte section ||style="color:DarkGrey;"| JP
|-
|<code> <code>LDIX</code> </code>|| <code>ED A4</code> || 16 || Extended LDI byte copy ||style="color:DarkGrey;"| LDIX
|-
|<code> <code>LDWS</code> </code>|| <code>ED A5</code> || 14 || Byte copy as for Layer 2 ||style="color:DarkGrey;"| LDWS
|-
|<code> <code>LDDX</code> </code>|| <code>ED AC</code> || 16 || Extended LDD byte copy ||style="color:DarkGrey;"| LDDX
|-
|<code> <code>LDIRX</code> </code>|| <code>ED B4</code> || 21/16 || Extended LDIR || LIRX
|-
|<code> <code>LDPIRX</code> </code>|| <code>ED B7</code> || 21/16 || Byte copy as for a pattern fill || LPRX
|-
|<code> <code>LDDRX</code> </code>|| <code>ED BC</code> || 21/16 || Extended LDDR || LDRX
|}

More details and the explanations of all Z80 instructions implemented in the Next Z80 CPU follow.

Notes:

* The encoding of the operand of the <code>PUSH $im16</code> is unique: it is the only operand encoded as big-endian.
* The timings (T-States) are based on some limited testing and may not be accurate.
* The shorter aliases of the official mnemonics (the 4-letter column) are those suggested in an initiative led by Matt Davies, the author of Odin assembler, editor and debugger tool for ZX Next.
* A relevant early source for this table could be [https://github.com/z88dk/z88dk/issues/312#issuecomment-322659205 a Christmas 2018 edit of a comment in a discussion of an issue 312 of z88dk].

=== Notation ===
* In the descriptions ''any 8-bit register'' means A, B, C, D, E, H, and L. The registers named F, I and R aren't a part of this set even if they are technically 8 bit registers. Additionally, IXH, IXL, IYH, IYL, which are the high and low byte parts of IX and IY, can be used in some of the instructions as 8-bit registers although this wasn't documented for the original Z80.
* IXY means IX or IY.
* For the status field:
** S means Standard. It's in the Z80 manual. Everything should support it.
** U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
** E means Extension. It ''only'' works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
* Each of the flag effects is documented as follows:
** - means the flag is unchanged.
** 1 or 0 mean the flag is set or reset as appropriate.
** ? means we don't know what effect the instruction has on the flag.
** ! means the instruction has an unusual effect on the flag which is documented in the description.
** S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
** P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it checks BC as loop counter for some of the block copy and search instructions: P/V = (BC != 0)

=== Register and Data manipulation ===
;LD (LoaD)

{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LD r, r' </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||r := r'
|-
|<code>LD r,n </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||7 ||r := n
|-
|<code>LD r, (HL) </code>||Register ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||r := HL*
|-
|<code>LD r, (IXY+d) </code>||Register ||Indexed ||S ||- ||- ||- ||- ||- ||- ||19 ||r := (IXY+d)*
|-
|<code>LD (HL),r </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||7 ||HL* := r
|-
|<code>LD (IXY+d),r </code>||Indexed ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+D)* := r
|-
|<code>LD (HL), n </code>||Indirect ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||HL* := n
|-
|<code>LD (IXY+d), n </code>||Indexed ||Immediate ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+d)* := n
|-
|<code>LD A, (BC/DE) </code>||Accumulator ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||A := rr*
|-
|<code>LD A, (nn) </code>||Accumulator ||Address ||S ||- ||- ||- ||- ||- ||- ||13 ||A := (nn)*
|-
|<code>LD (BC/DE), A </code>||Indirect ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||7 ||rr* := A
|-
|<code>LD (nn), A </code>||Address ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||13 ||(nn)* := A
|-
|<code>LD A, I </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := I; P/V:=IFF2
|-
|<code>LD A, R </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := R; P/V:=IFF2
|-
|<code>LD I, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||I := A
|-
|<code>LD R, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||R := A
|-
|<code>LD BC/DE/HL/SP, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||rr := nn
|-
|<code>LD IXY, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||14 ||rr := nn
|-
|<code>LD HL, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||16 ||HL := (nn)*
|-
|<code>LD BC/DE/SP/IXY, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||20 ||rr := (nn)*
|-
|<code>LD (nn), HL </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||16 ||(nn)* := HL
|-
|<code>LD (nn), BC/DE/SP/IXY </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||20 ||(nn)* := rr
|-
|<code>LD SP, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||6 ||SP := HL
|-
|<code>LD SP, IXY </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||10 ||SP := IXY
|}
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
:* Any 8-bit register can be:
:** loaded with an immediate value;
:** loaded with the contents of any other 8-bit register except I and R;
:** loaded with the contents of, or stored in, memory pointed to by HL;
:** loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
:* Additionally, the accumulator A (only) can be:
:** loaded with the contents of, or stored in, memory pointed to by BC or DE;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address;
:** loaded with the contents of I or R.
:* Any 16-bit register pair can be:
:** loaded with an immediate value;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address.
:* Additionally, SP (only) can be:
:** loaded with the contents of HL, IX, or IY.
:** The planned '''ld hl, sp''' didn't make it to Next yet, one possible workaround is: '''ld hl,0'''; '''add hl,sp''';
:* Memory referred to by HL or through IX can be assigned immediate values.
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
:LD instructions do not alter any flags unless I or R are loaded into A.

;EX (EXchange)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EX DE, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(DE,HL)
|-
|<code>EX AF, AF' </code>||Register ||Register ||S ||! ||! ||! ||! ||! ||! ||4 ||swap(AF,AF')
|-
|<code>EX (SP), HL </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||swap(SP*,HL)
|-
|<code>EX (SP), IXY </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||23 ||swap(SP*,IXY)
|}
:Exchanges the contents of two sources. The only permitted combinations are
:* Exchanging DE and HL;
:* Exchanging AF and AF';
:* Exchanging HL, IX, or IY with the contents of memory pointed to by SP.

;EXX (EXchange all)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EXX </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(BC,BC');swap(DE,DE');swap(HL,HL')
|}
:Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.

;PUSH
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PUSH BC/DE/HL/AF </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||SP-=2; SP*:=rr
|-
|<code>PUSH IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||15 ||SP-=2; SP*:=rr
|-
|<code>PUSH nn </code>||Immediate ||- ||E ||- ||- ||- ||- ||- ||- ||23 ||SP-=2; SP*:=nn
|}
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.

;POP
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>POP BC/DE/HL </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr:=SP*; SP+=2
|-
|<code>POP AF </code>||Register ||- ||S ||! ||! ||! ||! ||! ||! ||10 ||rr:=SP*; SP+=2
|-
|<code>POP IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||rr:=SP*; SP+=2
|}
:Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.
:Popping into AF does set value of flag register F directly to low 8 bits of value from stack.

=== Block Copy ===
;LDI (LoaD and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDI </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE++; HL++; BC--
|}
:Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;LDIR (LoaD and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIR </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||21x+16 ||do LDI while(BC>0)
|}
:Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).
:Flag effects are the same as LDI except that P/V will always be reset, because BC by definition reaches 0 before this instruction ends (normally - unless something overwrites LDIR opcode while BC>0).
:Interrupts may interrupt LDIR instruction while looping (after each single LDI sub-part finished) and LDIR will resume after and finish loop properly.

;LDD (LoaD and Decrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDD </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE--; HL--; BC--
|}
:Same as LDI, but subtracts 1 from DE and HL instead of adding.

;LDDR (LoaD and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDDR </code>||- ||- ||S ||- ||0 ||0 ||0 ||- ||- ||21x+16 ||do LDD while(BC>0)
|}
:Same as LDIR but loops LDD instead of LDI.

;LDWS
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDWS </code>||- ||- ||E ||- ||0 ||! ||S ||S ||S ||14 ||DE*:=HL*; INC L; INC D;
|}
:Next-only extended opcode. Copies the byte pointed to by HL to the address pointed to by DE and increments only L and D. This is used for vertically copying bytes to the Layer 2 display.
:The flags are identical to what the '''INC D''' instruction would produce.
:Note the source data are read only from single 256B (aligned) block of memory, because only L is incremented, not HL.

;LDIX, LDIRX, LDDX, LDDRX
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL++; BC--
|-
|<code>LDIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDIX while(BC>0)
|-
|<code>LDDX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL--; BC--
|-
|<code>LDDRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDDX while(BC>0)
|}
:Next-only extended opcodes. Behave similarly as their non-X equivalents except the byte is not copied if it is equal to A and LDDX/LDDRX advance DE by incrementing it (like LDI), while HL is decremented (like LDD).
:Second difference to non-X instructions (as usual with next-only opcodes due to implementation), the extended ones don't modify any flags.

;LDPIRX
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDPIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
|}
:Similar to LDIRX except the source byte address is not just HL, but is obtained by using the top 13 bits of HL and the lower 3 bits of DE and HL does not increment during whole loop (HL works as base address of aligned 8 byte lookup table, DE works as destination and also wrapping index 0..7 into table). This is intended for "pattern fill" functionality.

=== Block Search ===
;CPI (ComPare and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPI </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL++; BC--
|}
:Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;CPIR (ComPare and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPIR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPI while (!Z && BC>0)
|}
:Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0).
:Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.

;CPD (ComPare and Decrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPD </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL--; BC--
|}
:Same as CPI, but subtracts 1 from HL instead of adding it.

;CPDR (ComPare and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPDR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPD while (!Z && BC>0)
|}
:Same as CPIR but loops CPD instead of CPI.

=== Arithmetic ===
;ADD
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADD A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r
|-
|<code>ADD A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n
|-
|<code>ADD A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*
|-
|<code>ADD A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*
|-
|<code>ADD HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||11 ||HL+=rr
|-
|<code>ADD IXY, BC/DE/IXY/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||15 ||IXY+=rr
|-
|<code>ADD HL/DE/BC, A </code>||Register ||Register ||E ||? ||- ||- ||- ||- ||- ||8 ||rr+=unsigned A
|-
|<code>ADD HL/DE/BC, nn </code>||Register ||Immediate ||E ||- ||- ||- ||- ||- ||- ||16 ||rr+=nn
|}
:Adds values together. Legal combinations are:
:* When adding 8-bit values the first parameter must be A and the second may be:
:** The contents of an 8-bit register;
:** An immediate value;
:** The contents of memory pointed to by HL or by indexing based on IX or IY.
:* When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register.
:* For 16 bit additions (regular Z80), H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)
:* On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A (A will be zero extended to 16 bits) or an 16bit immediate value.

;ADC (ADd with Carry)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADC A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r+(CF?1:0)
|-
|<code>ADC A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n+(CF?1:0)
|-
|<code>ADC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*+(CF?1:0)
|-
|<code>ADC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*+(CF?1:0)
|-
|<code>ADC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||V ||! ||S ||S ||15 ||HL+=rr+(CF?1:0)
|}
:Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if carry from bit 11; otherwise, it is reset.

;SUB
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SUB r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A -= r
|-
|<code>SUB n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= n
|-
|<code>SUB (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= HL*
|-
|<code>SUB (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A -= (IXY+d)*
|}
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.

;SBC (SuBtract with Carry, er, borrow)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SBC A, r </code>||Accumulator ||Register ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=(r+(CF?1:0))
|-
|<code>SBC A, n </code>||Accumulator ||Immediate ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(n+(CF?1:0))
|-
|<code>SBC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(HL*+(CF?1:0))
|-
|<code>SBC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=((IXY+d)+(CF?1:0))
|-
|<code>SBC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||1 ||V ||! ||S ||S ||15 ||HL-=(rr+(CF?1:0))
|}
:Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset.

;AND, OR, XOR
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>AND r </code>||Register ||- ||S ||0 ||0 ||P ||1 ||S ||S ||4 ||A := A & r
|-
|<code>AND n </code>||Immediate ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & n
|-
|<code>AND (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & HL*
|-
|<code>AND (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||1 ||S ||S ||19 ||A := A & (IXY+d)*
|-
|<code>OR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A OR r
|-
|<code>OR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR n
|-
|<code>OR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR HL*
|-
|<code>OR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A OR (IXY+d)*
|-
|<code>XOR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A ^ r
|-
|<code>XOR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ n
|-
|<code>XOR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ HL*
|-
|<code>XOR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A ^ (IXY+d)*
|}
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.

:XOR A is faster and shorter than LD A,0

;MIRROR
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MIRROR A </code>||Register ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A[76543210]:=A[01234567]
|}
:Next extended opcode. Mirrors (reverses the order) of bits in the accumulator. Older core versions supported MIRROR DE, but this was removed.

;CP (ComPare)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CP r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=r?
|-
|<code>CP n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=n?
|-
|<code>CP (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=HL*?
|-
|<code>CP (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=(IXY+d)?
|}
:Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
:* CP is ''not'' equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.

;TEST
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>TEST n </code>||Immediate ||- ||E ||S ||? ||P ||S ||S ||S ||11 ||A&n?
|}
: Next extended opcode. Similar to CP, but performs an AND instead of a subtraction.

;INC (INCrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INC r </code>||Register ||- ||S ||- ||0 ||! ||S ||S ||S ||4 ||r++
|-
|<code>INC (HL) </code>||Indirect ||- ||S ||- ||0 ||! ||S ||S ||S ||11 ||HL*++
|-
|<code>INC (IXY+d) </code>||Indexed ||- ||S ||- ||0 ||! ||S ||S ||S ||23 ||(IXY+d)*++
|-
|<code>INC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr++
|-
|<code>INC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr++
|}
:Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
:* INC A is faster than ADD 1.

;DEC (DECrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DEC r </code>||Register ||- ||S ||- ||1 ||! ||S ||S ||S ||4 ||r--
|-
|<code>DEC (HL) </code>||Indirect ||- ||S ||- ||1 ||! ||S ||S ||S ||11 ||HL*--
|-
|<code>DEC (IXY+d) </code>||Indexed ||- ||S ||- ||1 ||! ||S ||S ||S ||23 ||(IXY+D)*--
|-
|<code>DEC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr--
|-
|<code>DEC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr--
|}
:Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
:* DEC A is faster than SUB 1.

;RLC (Rotate Left Circular)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=x; CF:=x
|-
|<code>RLC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=x; CF:=x
|-
|<code>RLC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=x; CF:=x
|-
|<code>RLC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=x; CF:=x; r:=(IX+d)*
|}
:Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.

;RL (Rotate Left)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x
|-
|<code>RL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=CF; CF:=x
|-
|<code>RL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=CF; CF:=x
|-
|<code>RL r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=CF; CF:=x; r:=(IX+d)*
|}
:Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.

;RRC, RR (Rotate Right Circular, Rotate Right)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=x; CF:=x
|-
|<code>RRC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=x; CF:=x
|-
|<code>RRC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=x; CF:=x
|-
|<code>RRC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=x; CF:=x; r:=(IX+d)*
|-
|<code>RR r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x
|-
|<code>RR (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=CF; CF:=x
|-
|<code>RR (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=CF; CF:=x
|-
|<code>RR r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=CF; CF:=x; r=(IX+d)*
|}
:Same as RLC and RL except they rotate right instead of left.

;SLA (Shift Left Arithmetic)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SLA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r<<1
|-
|<code>SLA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*<<1
|-
|<code>SLA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*<<1
|-
|<code>SLA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*<<1; r=(IX+d)*
|}
:Same as RL except bit 0 is set to zero, not the previous contents of Carry.

;SRA (Shift Right Arithmetic)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r>>1 OR r[7]
|-
|<code>SRA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*>>1 OR HL*[7]
|-
|<code>SRA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*>>1 OR (IXY+d)*[7]
|-
|<code>SRA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*>>1 OR (IX+d)*[7]; r:=(IX+d)*
|}
:Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry.

;SRL (Shift Right Logical)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||0 ||8 ||r:=unsigned(r)>>1
|-
|<code>SRL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||0 ||15 ||HL*:=unsigned(HL*)>>1
|-
|<code>SRL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1
|-
|<code>SRL r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1; r:=(IXY+d)*
|}
:Same as SLA except it shifts right instead of left.

;RLCA, RLA, RRCA, RRA
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=x; CF:=x
|-
|<code>RLA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x
|-
|<code>RRCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=x; CF:=x
|-
|<code>RRA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x
|}
:Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.

;SLL (Shift Left Logical)
:This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.

;SL1 or SLI (Shift Left and Add 1) or (Shift Left and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SL1 r </code>||Register ||- ||U ||! ||0 ||P ||0 ||S ||S ||8 ||r:=(r<<1)+1
|-
|<code>SL1 (HL) </code>||Indirect ||- ||U ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=(HL*<<1)+1
|-
|<code>SL1 (IXY+d) </code>||Indexed ||- ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1
|-
|<code>SL1 r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1; r=(IXY+d)*
|}
:Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.

;RLD (Rotate Left bcd Digit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]
|}
:Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.

;RRD (Rotate Right bcd Digit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]
|}
:Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.

;Barrel (variable amount) shift and rotate (cores v2+ only)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BSLA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&31) ||8
|-
|<code>BSRA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=signed(DE)>>(B&31) ||8
|-
|<code>BSRL DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=unsigned(DE)>>(B&31) ||8
|-
|<code>BSRF DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=~(unsigned(~DE)>>(B&31)) ||8
|-
|<code>BRLC DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&15) OR DE>>(16-B&15) ||8
|}
:Shift instructions use only bits 4..0 of B, BSLA shifts DE left, BSRA/BSRL/BSRF shifts DE right in arithmetic/logical/fill-one way. BRLC rotates DE left by B places, uses only bits 3..0 of B (to rotate right, use B=16-places).

If you are implementing BSRF in C (or similar), be careful with implicit variable type promotion. You will need to do something like this: DE:=~((uint16_t)~DE>>(B&31))

;CPL (ComPLement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPL </code>||- ||- ||S ||- ||1 ||- ||1 ||- ||- ||4 ||A:=~A
|}
:Inverts the contents of the accumulator.

;NEG (NEGate)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEG </code>||- ||- ||S ||! ||1 ||! ||S ||S ||S ||8 ||A:=0-A
|}
:Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.

;CCF (Complement Carry Flag)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CCF </code>||- ||- ||S ||! ||0 ||- ||! ||- ||- ||4 ||CF:=!CF
|}
:Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.

;SCF (Set Carry Flag)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SCF </code>||- ||- ||S ||1 ||0 ||- ||0 ||- ||- ||4 ||CF:=1
|}
:Sets the carry flag.

;BIT (test BIT)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BIT b,r </code>||Immediate ||Register ||S ||- ||0 ||? ||1 ||! ||? ||8 ||r[b]==1?
|-
|<code>BIT b,(HL) </code>||Immediate ||Indirect ||S ||- ||0 ||? ||1 ||! ||? ||12 ||HL*[b]==1?
|-
|<code>BIT b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||0 ||? ||1 ||! ||? ||20 ||(IXY+d)*[b]==1?
|}
:Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.

;SET (SET bit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SET b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r OR (1<<b)
|-
|<code>SET b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* OR (1<<b)
|-
|<code>SET b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* OR (1<<b)
|-
|<code>SET r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* OR (1<<b); r:=(IX+d)*
|-
|<code>SETAE </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=unsigned($80)>>(E&7)
|}
:Sets the numbered bit on target value. The possible targets are the same as BIT. The three parameter variant is undocumented and stores the result in a register as well as performing the SET.
:SETAE is a Next extended opcode which takes the bit number to set from E (only the low 3 bits) and sets whole A to value of that bit, but counted from top to bottom (E=0 will produce A:=$80, E=7 will produce A:=$01). This works as pixel mask for ULA bitmap modes, when E is 0..255 x-coordinate.

;RES (RESet bit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RES b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r & (~(1<<b))
|-
|<code>RES b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* & (~(1<<b))
|-
|<code>RES b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* & (~(1<<b))
|-
|<code>RES r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* & (~(1<<b)); r:=(IX+d)*
|}
:Resets the numbered bit on target value. The possible targets are the same as BIT.

;DAA (Decimal Adjust Accumulator)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DAA </code>||- ||- ||S ||! ||- ||P ||! ||S ||S ||8 ||if(A&$0F>$09 or HF) A±=$06; if(A&$F0>$90 or CF) A±=$60 (± depends on NF)
|}
:Modifies the contents of the accumulator based on the flags left by previous operation to correct for binary coded decimal (BCD).

;MUL (MULtiply)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MUL d,e </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||DE:=D*E
|}
:Next extended opcode. Multiplies D by E, storing 16 bit result into DE. Does not alter any flags (the opcode is not compatible with any of the R800/Z180/eZ80/... variants of MUL, it is solely Next specific).

;SWAPNIB (SWAP NIBbles)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SWAPNIB </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=A[3210]<<4 OR A[7654]>>4
|}
:Next extended opcode. Swaps the high and low nibbles of the accumulator.

;PIXELAD (PIXEL ADdress)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELAD </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
|}
:Next extended opcode. Takes E and D as the X,Y coordinate of a point and calculates the address of the byte containing this pixel in the pixel area of standard ULA screen 0, storing it in HL.

;PIXELDN (PIXEL DowN)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELDN </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||if(HL&$0700!=$0700) HL+=256; 
else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; 
else HL:=HL&$F81F+$0800
|}
:Updates the address in HL to move down by one line of pixels.

=== Control Flow ===
;JP (JumP)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=nn
|-
|<code>JP (HL) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC:=HL (not PC:=HL*)
|-
|<code>JP (IXY) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||PC:=IXY (not PC:=IXY*)
|-
|<code>JP (C) </code>||Register ||- ||E ||? ||? ||? ||? ||? ||? ||13 ||PC:=PC&$C000+IN(C)<<6
|}
:Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs ''look'' like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to. The JP (C) sets bottom 14 bits of current PC* to value read from I/O port: PC[13:0] = (IN (C) << 6) (can be used to execute code block read from a disk stream) * "current PC" is address of next instruction after JP (C), as the PC is advanced by fetching op code from memory and is already advanced when execution happens - if the JP instruction resides at the very end of 16k memory block (..FE or ..FF address), then newly composed PC value will land into following 16k block.

;JP cc (JumP conditionally)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP Z/NZ/NC/C/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||if cc PC:=nn
|}
:Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.

;JR (Jump Relative)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JR nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ||PC+=nn
|-
|<code>JR C/NC/Z/NZ, nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ; 7 if not cc ||if cc PC+=nn
|}
:Jumps to an alternate address by ''adding'' the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.

;DJNZ (Decrement reg. b and Jump if Not Zero)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DJNZ n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||13 ||B--; if B!=0 PC+=nn
|}
:Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.

;CALL
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CALL nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ||SP-=2; SP*:=PC; PC:=nn
|-
|<code>CALL Z/NZ/C/NC/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ; 10 if not cc ||if cc {SP-=2; SP*:=PC; PC:=nn}
|}
:Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.
:* If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)

;RET (RETurn)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RET </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=SP*; SP+=2
|-
|<code>RET Z/NZ/C/NC/PO/PE/P/M </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||11 ; 5 if not cc ||if cc {PC:=SP*; SP+=2}
|}
:POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.

;RETI (RETurn from Interrupt)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||PC:=SP*; SP+=2
|}
:Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).

;RETN (RETurn from Non-maskable interrupt)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETN </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||IFF1:=IFF2; PC:=SP*; SP+=2
|}
:Returns from a non-maskable interrupt service routine.

;RST (ReSTart)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RST n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||CALL n
|}
:Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.

;NOP (No OPeration)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NOP </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC+=1
|}
:Does "nothing" (just usual housekeeping like refreshing memory and advancing program counter to next instruction).

;HALT
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>HALT </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||waits for interrupt
|}
:Suspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.

;DI (Disable Interrupts)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=0; IFF2:=0
|}
:Disables maskable interrupts.

;EI (Enable Interrupts)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=1; IFF2:=1
|}
:Enables maskable interrupts (after next instruction, i.e. for example "EI RET" - the interrupt may happen only after RET instruction is finished (or "EI DI" pair of instructions will not allow any maskable interrupt to happen).

;IM (Interrupt Mode)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IM n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||Interrupt mode:=n
|}
:Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)

=== Input and Output ===
;IN r, (c); OUT (c), r
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN r, (c) </code>||Register ||Register ||S ||- ||0 ||P ||0 ||S ||S ||12 ||r := in(BC)
|-
|<code>OUT (c),r </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||12 ||out(BC,r)
|}
:Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.

;IN (c); OUT (c), 0
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN (c) </code>||Register ||- ||U ||- ||0 ||P ||0 ||S ||S ||12 ||in(BC)?
|-
|<code>OUT (c),0 </code>||Register ||Immediate ||U ||- ||- ||- ||- ||- ||- ||12 ||out(BC,0)
|}
:Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode. The Next FPGA does output zero, but some Z80 chips manufactured differently from early batches output different value like 255, so it is not recommended to use OUT (C),0 if you want to reuse your code also on classic ZX Spectrum or publish it as example.

;IN a, (n); OUT (n), a
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN A, (n) </code>||Accumulator ||Immediate ||S ||- ||- ||- ||- ||- ||- ||11 ||A := in(An)
|-
|<code>OUT (n),A </code>||Immediate ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||11 ||out(An,A)
|}
:Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.

;INI (INput and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL++; B--
|}
:Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.

;INIR (INput and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do INI while(B>0)
|}
:Loops INIR until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

;IND, INDR (INput and Decrement, INput and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IND </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL--; B--
|-
|<code>INDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do IND while(B>0)
|}
:Behave like INI and INIR except that HL is decremented instead of incremented.

;OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL++
|-
|<code>OTIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTI while (B>0)
|-
|<code>OUTD </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL--
|-
|<code>OTDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTD while (B>0)
|}
:Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented '''before''' the output instead of after. Condition check on B is performed '''after''', so that if OTIR starts with B=0 it loops 256 times.

;OUTINB (Out and Increment with No B)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTINB </code>||- ||- ||E ||? ||? ||? ||? ||? ||? ||16 ||out(BC,HL*); HL++
|}
:Next extended opcode. Behaves like OUTI, but doesn't decrement B.

;NEXTREG
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEXTREG n,n' </code>||Immediate ||Immediate ||E ||- ||- ||- ||- ||- ||- ||20 ||HwNextReg_n:=n'
|-
|<code>NEXTREG n, A </code>||Immediate ||Accumulator ||E ||- ||- ||- ||- ||- ||- ||17 ||HwNextReg_n:=A
|}
:Next extended opcode. Directly sets the [[Board feature control|Next Feature Control Registers]] without going through ports {{PortNo|$243B}} and {{PortNo|$253B}}.

=== A note on some Z80-N specific observations ===
2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.

2025-01-25: Testing 3.02.x 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

=== Errata ===

This section lists the changes of the specification of the behavior of Z80N instructions, compared to the previous content of this wiki page.

2022-01-11: The previous versions of this page didn't match what was [http://www.z80.info/zip/z80-documented.pdf documented] for several years, that regular Z80 INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR instructions do modify carry flag (contrary to the official Z80 documentation and many Internet resources describing Z80 instructions).

Extended Z80 instruction set

2025-10-07T11:58:52Z

Sol HSA: removed margin:auto

This is a general list of Z80 and Z80N instructions with descriptions. The instructions specific to Z80N have the [[#Z80N_instructions_opcodes|encodings described first]].

For a table of summaries without additional descriptions see the [[Z80 Instruction Table]]. There's also a [[Special:RunQuery/OpcodeQuery|special search for opcodes in the same table]] and an external [https://table.specnext.dev/ Z80N opcode value matrix on specnext.dev].

=== Z80N instructions opcodes ===

This is a table of the instructions and the encodings of all '''Next-specific''' Z80 instructions:

{| class="wikitable sortable"
|-
! Instruction !!data-sort-type="text"| Encoding (2-4 bytes) (hex) !! T-States !! Description !! 4 letter
|-
|<code> <code>SWAPNIB</code> </code>|| <code>ED 23</code> || 8 || Swap the nibbles (4-bits) of A || SWAP
|-
|<code> <code>MIRROR A</code> </code>|| <code>ED 24</code> || 8 || Mirror bits 0..7 to 7..0 of A || MIRR
|-
|<code> <code>TEST $im8</code> </code>|| <code>ED 27</code> value || 11 || Change flags as AND A but A stays unaffected ||style="color:DarkGrey;"| TEST
|-
|<code> <code>BSLA DE,B</code> </code>|| <code>ED 28</code> || 8 || Shift left DE for B bits ||style="color:DarkGrey;"| BSLA
|-
|<code> <code>BSRA DE,B</code> </code>|| <code>ED 29</code> || 8 || Shift right signed DE for B bits ||style="color:DarkGrey;"| BSRA
|-
|<code> <code>BSRL DE,B</code> </code>|| <code>ED 2A</code> || 8 || Shift right DE for B bits ||style="color:DarkGrey;"| BSRL
|-
|<code> <code>BSRF DE,B</code> </code>|| <code>ED 2B</code> || 8 || Shift right DE, filling 1 for B bits ||style="color:DarkGrey;"| BSRF
|-
|<code> <code>BRLC DE,B</code> </code>|| <code>ED 2C</code> || 8 || Rotate left DE for B bits ||style="color:DarkGrey;"| BRLC
|-
|<code> <code>MUL D,E</code> </code>|| <code>ED 30</code> || 8 || Multiply D with E, result in DE ||style="color:DarkGrey;"| MUL
|-
|<code> <code>ADD HL,A</code> </code>|| <code>ED 31</code> || 8 || Add unsigned A to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,A</code> </code>|| <code>ED 32</code> || 8 || Add unsigned A to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,A</code> </code>|| <code>ED 33</code> || 8 || Add unsigned A to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD HL,$im16</code> </code>|| <code>ED 34 low high</code> || 16 || Add a constant to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,$im16</code> </code>|| <code>ED 35 low high</code> || 16 || Add a constant to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,$im16</code> </code>|| <code>ED 36 low high</code> || 16 || Add a constant to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>PUSH $im16</code> </code>|| <code>ED 8A high low</code> || 23 || Push a constant ||style="color:DarkGrey;"| PUSH
|-
|<code> <code>OUTINB</code> </code>|| <code>ED 90</code> || 16 || OUTI, but don't change B || OTIB
|-
|<code> <code>NEXTREG $im8,$im8</code> </code>|| <code>ED 91 register value</code> || 20 || Write v to Next register r || NREG
|-
|<code> <code>NEXTREG $im8,A</code> </code>|| <code>ED 92 register</code> || 17 || Write A to Next register r || NREG
|-
|<code> <code>PIXELDN</code> </code>|| <code>ED 93</code> || 8 || HL as a pixel address moved one line down || PXDN
|-
|<code> <code>PIXELAD</code> </code>|| <code>ED 94</code> || 8 || HL := as ULA pixel address from D==Y E==X || PXAD
|-
|<code> <code>SETAE</code> </code>|| <code>ED 95</code> || 8 || Get A as a mask for ULA pixel from E || STAE
|-
|<code> <code>JP (C)</code> </code>|| <code>ED 98</code> || 13 || IN (C) then jump to a 64 byte section ||style="color:DarkGrey;"| JP
|-
|<code> <code>LDIX</code> </code>|| <code>ED A4</code> || 16 || Extended LDI byte copy ||style="color:DarkGrey;"| LDIX
|-
|<code> <code>LDWS</code> </code>|| <code>ED A5</code> || 14 || Byte copy as for Layer 2 ||style="color:DarkGrey;"| LDWS
|-
|<code> <code>LDDX</code> </code>|| <code>ED AC</code> || 16 || Extended LDD byte copy ||style="color:DarkGrey;"| LDDX
|-
|<code> <code>LDIRX</code> </code>|| <code>ED B4</code> || 21/16 || Extended LDIR || LIRX
|-
|<code> <code>LDPIRX</code> </code>|| <code>ED B7</code> || 21/16 || Byte copy as for a pattern fill || LPRX
|-
|<code> <code>LDDRX</code> </code>|| <code>ED BC</code> || 21/16 || Extended LDDR || LDRX
|}

More details and the explanations of all Z80 instructions implemented in the Next Z80 CPU follow.

Notes:

* The encoding of the operand of the <code>PUSH $im16</code> is unique: it is the only operand encoded as big-endian.
* The timings (T-States) are based on some limited testing and may not be accurate.
* The shorter aliases of the official mnemonics (the 4-letter column) are those suggested in an initiative led by Matt Davies, the author of Odin assembler, editor and debugger tool for ZX Next.
* A relevant early source for this table could be [https://github.com/z88dk/z88dk/issues/312#issuecomment-322659205 a Christmas 2018 edit of a comment in a discussion of an issue 312 of z88dk].

=== Notation ===
* In the descriptions ''any 8-bit register'' means A, B, C, D, E, H, and L. The registers named F, I and R aren't a part of this set even if they are technically 8 bit registers. Additionally, IXH, IXL, IYH, IYL, which are the high and low byte parts of IX and IY, can be used in some of the instructions as 8-bit registers although this wasn't documented for the original Z80.
* IXY means IX or IY.
* For the status field:
** S means Standard. It's in the Z80 manual. Everything should support it.
** U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
** E means Extension. It ''only'' works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
* Each of the flag effects is documented as follows:
** - means the flag is unchanged.
** 1 or 0 mean the flag is set or reset as appropriate.
** ? means we don't know what effect the instruction has on the flag.
** ! means the instruction has an unusual effect on the flag which is documented in the description.
** S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
** P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it checks BC as loop counter for some of the block copy and search instructions: P/V = (BC != 0)

=== Register and Data manipulation ===
;LD (LoaD)

{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LD r, r' </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||r := r'
|-
|<code>LD r,n </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||7 ||r := n
|-
|<code>LD r, (HL) </code>||Register ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||r := HL*
|-
|<code>LD r, (IXY+d) </code>||Register ||Indexed ||S ||- ||- ||- ||- ||- ||- ||19 ||r := (IXY+d)*
|-
|<code>LD (HL),r </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||7 ||HL* := r
|-
|<code>LD (IXY+d),r </code>||Indexed ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+D)* := r
|-
|<code>LD (HL), n </code>||Indirect ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||HL* := n
|-
|<code>LD (IXY+d), n </code>||Indexed ||Immediate ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+d)* := n
|-
|<code>LD A, (BC/DE) </code>||Accumulator ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||A := rr*
|-
|<code>LD A, (nn) </code>||Accumulator ||Address ||S ||- ||- ||- ||- ||- ||- ||13 ||A := (nn)*
|-
|<code>LD (BC/DE), A </code>||Indirect ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||7 ||rr* := A
|-
|<code>LD (nn), A </code>||Address ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||13 ||(nn)* := A
|-
|<code>LD A, I </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := I; P/V:=IFF2
|-
|<code>LD A, R </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := R; P/V:=IFF2
|-
|<code>LD I, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||I := A
|-
|<code>LD R, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||R := A
|-
|<code>LD BC/DE/HL/SP, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||rr := nn
|-
|<code>LD IXY, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||14 ||rr := nn
|-
|<code>LD HL, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||16 ||HL := (nn)*
|-
|<code>LD BC/DE/SP/IXY, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||20 ||rr := (nn)*
|-
|<code>LD (nn), HL </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||16 ||(nn)* := HL
|-
|<code>LD (nn), BC/DE/SP/IXY </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||20 ||(nn)* := rr
|-
|<code>LD SP, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||6 ||SP := HL
|-
|<code>LD SP, IXY </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||10 ||SP := IXY
|}
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
:* Any 8-bit register can be:
:** loaded with an immediate value;
:** loaded with the contents of any other 8-bit register except I and R;
:** loaded with the contents of, or stored in, memory pointed to by HL;
:** loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
:* Additionally, the accumulator A (only) can be:
:** loaded with the contents of, or stored in, memory pointed to by BC or DE;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address;
:** loaded with the contents of I or R.
:* Any 16-bit register pair can be:
:** loaded with an immediate value;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address.
:* Additionally, SP (only) can be:
:** loaded with the contents of HL, IX, or IY.
:** The planned '''ld hl, sp''' didn't make it to Next yet, one possible workaround is: '''ld hl,0'''; '''add hl,sp''';
:* Memory referred to by HL or through IX can be assigned immediate values.
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
:LD instructions do not alter any flags unless I or R are loaded into A.

;EX (EXchange)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EX DE, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(DE,HL)
|-
|<code>EX AF, AF' </code>||Register ||Register ||S ||! ||! ||! ||! ||! ||! ||4 ||swap(AF,AF')
|-
|<code>EX (SP), HL </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||swap(SP*,HL)
|-
|<code>EX (SP), IXY </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||23 ||swap(SP*,IXY)
|}
:Exchanges the contents of two sources. The only permitted combinations are
:* Exchanging DE and HL;
:* Exchanging AF and AF';
:* Exchanging HL, IX, or IY with the contents of memory pointed to by SP.

;EXX (EXchange all)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EXX </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(BC,BC');swap(DE,DE');swap(HL,HL')
|}
:Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.

;PUSH
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PUSH BC/DE/HL/AF </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||SP-=2; SP*:=rr
|-
|<code>PUSH IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||15 ||SP-=2; SP*:=rr
|-
|<code>PUSH nn </code>||Immediate ||- ||E ||- ||- ||- ||- ||- ||- ||23 ||SP-=2; SP*:=nn
}}

|}
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.

;POP
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>POP BC/DE/HL </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr:=SP*; SP+=2
|-
|<code>POP AF </code>||Register ||- ||S ||! ||! ||! ||! ||! ||! ||10 ||rr:=SP*; SP+=2
|-
|<code>POP IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||rr:=SP*; SP+=2
|}
:Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.
:Popping into AF does set value of flag register F directly to low 8 bits of value from stack.

=== Block Copy ===
;LDI (LoaD and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDI </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE++; HL++; BC--
|}
:Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;LDIR (LoaD and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIR </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||21x+16 ||do LDI while(BC>0)
|}
:Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).
:Flag effects are the same as LDI except that P/V will always be reset, because BC by definition reaches 0 before this instruction ends (normally - unless something overwrites LDIR opcode while BC>0).
:Interrupts may interrupt LDIR instruction while looping (after each single LDI sub-part finished) and LDIR will resume after and finish loop properly.

;LDD (LoaD and Decrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDD </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE--; HL--; BC--
|}
:Same as LDI, but subtracts 1 from DE and HL instead of adding.

;LDDR (LoaD and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDDR </code>||- ||- ||S ||- ||0 ||0 ||0 ||- ||- ||21x+16 ||do LDD while(BC>0)
|}
:Same as LDIR but loops LDD instead of LDI.

;LDWS
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDWS </code>||- ||- ||E ||- ||0 ||! ||S ||S ||S ||14 ||DE*:=HL*; INC L; INC D;
|}
:Next-only extended opcode. Copies the byte pointed to by HL to the address pointed to by DE and increments only L and D. This is used for vertically copying bytes to the Layer 2 display.
:The flags are identical to what the '''INC D''' instruction would produce.
:Note the source data are read only from single 256B (aligned) block of memory, because only L is incremented, not HL.

;LDIX, LDIRX, LDDX, LDDRX
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL++; BC--
|-
|<code>LDIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDIX while(BC>0)
|-
|<code>LDDX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL--; BC--
|-
|<code>LDDRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDDX while(BC>0)
|}
:Next-only extended opcodes. Behave similarly as their non-X equivalents except the byte is not copied if it is equal to A and LDDX/LDDRX advance DE by incrementing it (like LDI), while HL is decremented (like LDD).
:Second difference to non-X instructions (as usual with next-only opcodes due to implementation), the extended ones don't modify any flags.

;LDPIRX
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDPIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
|}
:Similar to LDIRX except the source byte address is not just HL, but is obtained by using the top 13 bits of HL and the lower 3 bits of DE and HL does not increment during whole loop (HL works as base address of aligned 8 byte lookup table, DE works as destination and also wrapping index 0..7 into table). This is intended for "pattern fill" functionality.

=== Block Search ===
;CPI (ComPare and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPI </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL++; BC--
|}
:Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;CPIR (ComPare and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPIR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPI while (!Z && BC>0)
|}
:Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0).
:Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.

;CPD (ComPare and Decrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPD </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL--; BC--
|}
:Same as CPI, but subtracts 1 from HL instead of adding it.

;CPDR (ComPare and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPDR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPD while (!Z && BC>0)
|}
:Same as CPIR but loops CPD instead of CPI.

=== Arithmetic ===
;ADD
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADD A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r
|-
|<code>ADD A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n
|-
|<code>ADD A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*
|-
|<code>ADD A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*
|-
|<code>ADD HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||11 ||HL+=rr
|-
|<code>ADD IXY, BC/DE/IXY/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||15 ||IXY+=rr
|-
|<code>ADD HL/DE/BC, A </code>||Register ||Register ||E ||? ||- ||- ||- ||- ||- ||8 ||rr+=unsigned A
|-
|<code>ADD HL/DE/BC, nn </code>||Register ||Immediate ||E ||- ||- ||- ||- ||- ||- ||16 ||rr+=nn
|}
:Adds values together. Legal combinations are:
:* When adding 8-bit values the first parameter must be A and the second may be:
:** The contents of an 8-bit register;
:** An immediate value;
:** The contents of memory pointed to by HL or by indexing based on IX or IY.
:* When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register.
:* For 16 bit additions (regular Z80), H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)
:* On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A (A will be zero extended to 16 bits) or an 16bit immediate value.

;ADC (ADd with Carry)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADC A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r+(CF?1:0)
|-
|<code>ADC A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n+(CF?1:0)
|-
|<code>ADC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*+(CF?1:0)
|-
|<code>ADC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*+(CF?1:0)
|-
|<code>ADC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||V ||! ||S ||S ||15 ||HL+=rr+(CF?1:0)
|}
:Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if carry from bit 11; otherwise, it is reset.

;SUB
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SUB r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A -= r
|-
|<code>SUB n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= n
|-
|<code>SUB (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= HL*
|-
|<code>SUB (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A -= (IXY+d)*
|}
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.

;SBC (SuBtract with Carry, er, borrow)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SBC A, r </code>||Accumulator ||Register ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=(r+(CF?1:0))
|-
|<code>SBC A, n </code>||Accumulator ||Immediate ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(n+(CF?1:0))
|-
|<code>SBC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(HL*+(CF?1:0))
|-
|<code>SBC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=((IXY+d)+(CF?1:0))
|-
|<code>SBC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||1 ||V ||! ||S ||S ||15 ||HL-=(rr+(CF?1:0))
|}
:Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset.

;AND, OR, XOR
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>AND r </code>||Register ||- ||S ||0 ||0 ||P ||1 ||S ||S ||4 ||A := A & r
|-
|<code>AND n </code>||Immediate ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & n
|-
|<code>AND (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & HL*
|-
|<code>AND (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||1 ||S ||S ||19 ||A := A & (IXY+d)*
|-
|<code>OR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A OR r
|-
|<code>OR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR n
|-
|<code>OR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR HL*
|-
|<code>OR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A OR (IXY+d)*
|-
|<code>XOR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A ^ r
|-
|<code>XOR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ n
|-
|<code>XOR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ HL*
|-
|<code>XOR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A ^ (IXY+d)*
|}
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.

:XOR A is faster and shorter than LD A,0

;MIRROR
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MIRROR A </code>||Register ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A[76543210]:=A[01234567]
|}
:Next extended opcode. Mirrors (reverses the order) of bits in the accumulator. Older core versions supported MIRROR DE, but this was removed.

;CP (ComPare)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CP r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=r?
|-
|<code>CP n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=n?
|-
|<code>CP (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=HL*?
|-
|<code>CP (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=(IXY+d)?
|}
:Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
:* CP is ''not'' equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.

;TEST
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>TEST n </code>||Immediate ||- ||E ||S ||? ||P ||S ||S ||S ||11 ||A&n?
|}
: Next extended opcode. Similar to CP, but performs an AND instead of a subtraction.

;INC (INCrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INC r </code>||Register ||- ||S ||- ||0 ||! ||S ||S ||S ||4 ||r++
|-
|<code>INC (HL) </code>||Indirect ||- ||S ||- ||0 ||! ||S ||S ||S ||11 ||HL*++
|-
|<code>INC (IXY+d) </code>||Indexed ||- ||S ||- ||0 ||! ||S ||S ||S ||23 ||(IXY+d)*++
|-
|<code>INC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr++
|-
|<code>INC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr++
|}
:Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
:* INC A is faster than ADD 1.

;DEC (DECrement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DEC r </code>||Register ||- ||S ||- ||1 ||! ||S ||S ||S ||4 ||r--
|-
|<code>DEC (HL) </code>||Indirect ||- ||S ||- ||1 ||! ||S ||S ||S ||11 ||HL*--
|-
|<code>DEC (IXY+d) </code>||Indexed ||- ||S ||- ||1 ||! ||S ||S ||S ||23 ||(IXY+D)*--
|-
|<code>DEC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr--
|-
|<code>DEC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr--
|}
:Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
:* DEC A is faster than SUB 1.

;RLC (Rotate Left Circular)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=x; CF:=x
|-
|<code>RLC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=x; CF:=x
|-
|<code>RLC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=x; CF:=x
|-
|<code>RLC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=x; CF:=x; r:=(IX+d)*
|}
:Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.

;RL (Rotate Left)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x
|-
|<code>RL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=CF; CF:=x
|-
|<code>RL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=CF; CF:=x
|-
|<code>RL r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=CF; CF:=x; r:=(IX+d)*
|}
:Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.

;RRC, RR (Rotate Right Circular, Rotate Right)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=x; CF:=x
|-
|<code>RRC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=x; CF:=x
|-
|<code>RRC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=x; CF:=x
|-
|<code>RRC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=x; CF:=x; r:=(IX+d)*
|-
|<code>RR r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x
|-
|<code>RR (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=CF; CF:=x
|-
|<code>RR (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=CF; CF:=x
|-
|<code>RR r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=CF; CF:=x; r=(IX+d)*
|}
:Same as RLC and RL except they rotate right instead of left.

;SLA (Shift Left Arithmetic)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SLA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r<<1
|-
|<code>SLA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*<<1
|-
|<code>SLA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*<<1
|-
|<code>SLA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*<<1; r=(IX+d)*
|}
:Same as RL except bit 0 is set to zero, not the previous contents of Carry.

;SRA (Shift Right Arithmetic)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r>>1 OR r[7]
|-
|<code>SRA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*>>1 OR HL*[7]
|-
|<code>SRA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*>>1 OR (IXY+d)*[7]
|-
|<code>SRA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*>>1 OR (IX+d)*[7]; r:=(IX+d)*
|}
:Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry.

;SRL (Shift Right Logical)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||0 ||8 ||r:=unsigned(r)>>1
|-
|<code>SRL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||0 ||15 ||HL*:=unsigned(HL*)>>1
|-
|<code>SRL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1
|-
|<code>SRL r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1; r:=(IXY+d)*
|}
:Same as SLA except it shifts right instead of left.

;RLCA, RLA, RRCA, RRA
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=x; CF:=x
|-
|<code>RLA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x
|-
|<code>RRCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=x; CF:=x
|-
|<code>RRA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x
|}
:Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.

;SLL (Shift Left Logical)
:This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.

;SL1 or SLI (Shift Left and Add 1) or (Shift Left and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SL1 r </code>||Register ||- ||U ||! ||0 ||P ||0 ||S ||S ||8 ||r:=(r<<1)+1
|-
|<code>SL1 (HL) </code>||Indirect ||- ||U ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=(HL*<<1)+1
|-
|<code>SL1 (IXY+d) </code>||Indexed ||- ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1
|-
|<code>SL1 r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1; r=(IXY+d)*
|}
:Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.

;RLD (Rotate Left bcd Digit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]
|}
:Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.

;RRD (Rotate Right bcd Digit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]
|}
:Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.

;Barrel (variable amount) shift and rotate (cores v2+ only)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BSLA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&31) ||8
|-
|<code>BSRA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=signed(DE)>>(B&31) ||8
|-
|<code>BSRL DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=unsigned(DE)>>(B&31) ||8
|-
|<code>BSRF DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=~(unsigned(~DE)>>(B&31)) ||8
|-
|<code>BRLC DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&15) OR DE>>(16-B&15) ||8
|}
:Shift instructions use only bits 4..0 of B, BSLA shifts DE left, BSRA/BSRL/BSRF shifts DE right in arithmetic/logical/fill-one way. BRLC rotates DE left by B places, uses only bits 3..0 of B (to rotate right, use B=16-places).

If you are implementing BSRF in C (or similar), be careful with implicit variable type promotion. You will need to do something like this: DE:=~((uint16_t)~DE>>(B&31))

;CPL (ComPLement)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPL </code>||- ||- ||S ||- ||1 ||- ||1 ||- ||- ||4 ||A:=~A
|}
:Inverts the contents of the accumulator.

;NEG (NEGate)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEG </code>||- ||- ||S ||! ||1 ||! ||S ||S ||S ||8 ||A:=0-A
|}
:Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.

;CCF (Complement Carry Flag)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CCF </code>||- ||- ||S ||! ||0 ||- ||! ||- ||- ||4 ||CF:=!CF
|}
:Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.

;SCF (Set Carry Flag)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SCF </code>||- ||- ||S ||1 ||0 ||- ||0 ||- ||- ||4 ||CF:=1
|}
:Sets the carry flag.

;BIT (test BIT)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BIT b,r </code>||Immediate ||Register ||S ||- ||0 ||? ||1 ||! ||? ||8 ||r[b]==1?
|-
|<code>BIT b,(HL) </code>||Immediate ||Indirect ||S ||- ||0 ||? ||1 ||! ||? ||12 ||HL*[b]==1?
|-
|<code>BIT b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||0 ||? ||1 ||! ||? ||20 ||(IXY+d)*[b]==1?
|}
:Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.

;SET (SET bit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SET b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r OR (1<<b)
|-
|<code>SET b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* OR (1<<b)
|-
|<code>SET b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* OR (1<<b)
|-
|<code>SET r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* OR (1<<b); r:=(IX+d)*
|-
|<code>SETAE </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=unsigned($80)>>(E&7)
|}
:Sets the numbered bit on target value. The possible targets are the same as BIT. The three parameter variant is undocumented and stores the result in a register as well as performing the SET.
:SETAE is a Next extended opcode which takes the bit number to set from E (only the low 3 bits) and sets whole A to value of that bit, but counted from top to bottom (E=0 will produce A:=$80, E=7 will produce A:=$01). This works as pixel mask for ULA bitmap modes, when E is 0..255 x-coordinate.

;RES (RESet bit)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RES b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r & (~(1<<b))
|-
|<code>RES b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* & (~(1<<b))
|-
|<code>RES b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* & (~(1<<b))
|-
|<code>RES r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* & (~(1<<b)); r:=(IX+d)*
|}
:Resets the numbered bit on target value. The possible targets are the same as BIT.

;DAA (Decimal Adjust Accumulator)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DAA </code>||- ||- ||S ||! ||- ||P ||! ||S ||S ||8 ||if(A&$0F>$09 or HF) A±=$06; if(A&$F0>$90 or CF) A±=$60 (± depends on NF)
|}
:Modifies the contents of the accumulator based on the flags left by previous operation to correct for binary coded decimal (BCD).

;MUL (MULtiply)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MUL d,e </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||DE:=D*E
|}
:Next extended opcode. Multiplies D by E, storing 16 bit result into DE. Does not alter any flags (the opcode is not compatible with any of the R800/Z180/eZ80/... variants of MUL, it is solely Next specific).

;SWAPNIB (SWAP NIBbles)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SWAPNIB </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=A[3210]<<4 OR A[7654]>>4
|}
:Next extended opcode. Swaps the high and low nibbles of the accumulator.

;PIXELAD (PIXEL ADdress)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELAD </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
|}
:Next extended opcode. Takes E and D as the X,Y coordinate of a point and calculates the address of the byte containing this pixel in the pixel area of standard ULA screen 0, storing it in HL.

;PIXELDN (PIXEL DowN)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELDN </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||if(HL&$0700!=$0700) HL+=256; 
else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; 
else HL:=HL&$F81F+$0800
|}
:Updates the address in HL to move down by one line of pixels.

=== Control Flow ===
;JP (JumP)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=nn
|-
|<code>JP (HL) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC:=HL (not PC:=HL*)
|-
|<code>JP (IXY) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||PC:=IXY (not PC:=IXY*)
|-
|<code>JP (C) </code>||Register ||- ||E ||? ||? ||? ||? ||? ||? ||13 ||PC:=PC&$C000+IN(C)<<6
|}
:Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs ''look'' like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to. The JP (C) sets bottom 14 bits of current PC* to value read from I/O port: PC[13:0] = (IN (C) << 6) (can be used to execute code block read from a disk stream) * "current PC" is address of next instruction after JP (C), as the PC is advanced by fetching op code from memory and is already advanced when execution happens - if the JP instruction resides at the very end of 16k memory block (..FE or ..FF address), then newly composed PC value will land into following 16k block.

;JP cc (JumP conditionally)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP Z/NZ/NC/C/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||if cc PC:=nn
|}
:Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.

;JR (Jump Relative)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JR nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ||PC+=nn
|-
|<code>JR C/NC/Z/NZ, nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ; 7 if not cc ||if cc PC+=nn
|}
:Jumps to an alternate address by ''adding'' the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.

;DJNZ (Decrement reg. b and Jump if Not Zero)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DJNZ n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||13 ||B--; if B!=0 PC+=nn
|}
:Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.

;CALL
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CALL nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ||SP-=2; SP*:=PC; PC:=nn
|-
|<code>CALL Z/NZ/C/NC/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ; 10 if not cc ||if cc {SP-=2; SP*:=PC; PC:=nn}
|}
:Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.
:* If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)

;RET (RETurn)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RET </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=SP*; SP+=2
|-
|<code>RET Z/NZ/C/NC/PO/PE/P/M </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||11 ; 5 if not cc ||if cc {PC:=SP*; SP+=2}
|}
:POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.

;RETI (RETurn from Interrupt)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||PC:=SP*; SP+=2
|}
:Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).

;RETN (RETurn from Non-maskable interrupt)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETN </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||IFF1:=IFF2; PC:=SP*; SP+=2
|}
:Returns from a non-maskable interrupt service routine.

;RST (ReSTart)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RST n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||CALL n
|}
:Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.

;NOP (No OPeration)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NOP </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC+=1
|}
:Does "nothing" (just usual housekeeping like refreshing memory and advancing program counter to next instruction).

;HALT
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>HALT </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||waits for interrupt
|}
:Suspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.

;DI (Disable Interrupts)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=0; IFF2:=0
|}
:Disables maskable interrupts.

;EI (Enable Interrupts)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=1; IFF2:=1
|}
:Enables maskable interrupts (after next instruction, i.e. for example "EI RET" - the interrupt may happen only after RET instruction is finished (or "EI DI" pair of instructions will not allow any maskable interrupt to happen).

;IM (Interrupt Mode)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IM n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||Interrupt mode:=n
|}
:Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)

=== Input and Output ===
;IN r, (c); OUT (c), r
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN r, (c) </code>||Register ||Register ||S ||- ||0 ||P ||0 ||S ||S ||12 ||r := in(BC)
|-
|<code>OUT (c),r </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||12 ||out(BC,r)
|}
:Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.

;IN (c); OUT (c), 0
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN (c) </code>||Register ||- ||U ||- ||0 ||P ||0 ||S ||S ||12 ||in(BC)?
|-
|<code>OUT (c),0 </code>||Register ||Immediate ||U ||- ||- ||- ||- ||- ||- ||12 ||out(BC,0)
|}
:Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode. The Next FPGA does output zero, but some Z80 chips manufactured differently from early batches output different value like 255, so it is not recommended to use OUT (C),0 if you want to reuse your code also on classic ZX Spectrum or publish it as example.

;IN a, (n); OUT (n), a
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN A, (n) </code>||Accumulator ||Immediate ||S ||- ||- ||- ||- ||- ||- ||11 ||A := in(An)
|-
|<code>OUT (n),A </code>||Immediate ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||11 ||out(An,A)
|}
:Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.

;INI (INput and Increment)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL++; B--
|}
:Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.

;INIR (INput and Increment Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do INI while(B>0)
|}
:Loops INIR until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

;IND, INDR (INput and Decrement, INput and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IND </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL--; B--
|-
|<code>INDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do IND while(B>0)
|}
:Behave like INI and INIR except that HL is decremented instead of incremented.

;OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL++
|-
|<code>OTIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTI while (B>0)
|-
|<code>OUTD </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL--
|-
|<code>OTDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTD while (B>0)
|}
:Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented '''before''' the output instead of after. Condition check on B is performed '''after''', so that if OTIR starts with B=0 it loops 256 times.

;OUTINB (Out and Increment with No B)
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTINB </code>||- ||- ||E ||? ||? ||? ||? ||? ||? ||16 ||out(BC,HL*); HL++
|}
:Next extended opcode. Behaves like OUTI, but doesn't decrement B.

;NEXTREG
{| class="wikitable"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEXTREG n,n' </code>||Immediate ||Immediate ||E ||- ||- ||- ||- ||- ||- ||20 ||HwNextReg_n:=n'
|-
|<code>NEXTREG n, A </code>||Immediate ||Accumulator ||E ||- ||- ||- ||- ||- ||- ||17 ||HwNextReg_n:=A
|}
:Next extended opcode. Directly sets the [[Board feature control|Next Feature Control Registers]] without going through ports {{PortNo|$243B}} and {{PortNo|$253B}}.

=== A note on some Z80-N specific observations ===
2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.

2025-01-25: Testing 3.02.x 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

=== Errata ===

This section lists the changes of the specification of the behavior of Z80N instructions, compared to the previous content of this wiki page.

2022-01-11: The previous versions of this page didn't match what was [http://www.z80.info/zip/z80-documented.pdf documented] for several years, that regular Z80 INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR instructions do modify carry flag (contrary to the official Z80 documentation and many Internet resources describing Z80 instructions).

Extended Z80 instruction set

2025-10-07T11:57:55Z

Sol HSA: rebuilt tables

This is a general list of Z80 and Z80N instructions with descriptions. The instructions specific to Z80N have the [[#Z80N_instructions_opcodes|encodings described first]].

For a table of summaries without additional descriptions see the [[Z80 Instruction Table]]. There's also a [[Special:RunQuery/OpcodeQuery|special search for opcodes in the same table]] and an external [https://table.specnext.dev/ Z80N opcode value matrix on specnext.dev].

=== Z80N instructions opcodes ===

This is a table of the instructions and the encodings of all '''Next-specific''' Z80 instructions:

{| class="wikitable sortable"
|-
! Instruction !!data-sort-type="text"| Encoding (2-4 bytes) (hex) !! T-States !! Description !! 4 letter
|-
|<code> <code>SWAPNIB</code> </code>|| <code>ED 23</code> || 8 || Swap the nibbles (4-bits) of A || SWAP
|-
|<code> <code>MIRROR A</code> </code>|| <code>ED 24</code> || 8 || Mirror bits 0..7 to 7..0 of A || MIRR
|-
|<code> <code>TEST $im8</code> </code>|| <code>ED 27</code> value || 11 || Change flags as AND A but A stays unaffected ||style="color:DarkGrey;"| TEST
|-
|<code> <code>BSLA DE,B</code> </code>|| <code>ED 28</code> || 8 || Shift left DE for B bits ||style="color:DarkGrey;"| BSLA
|-
|<code> <code>BSRA DE,B</code> </code>|| <code>ED 29</code> || 8 || Shift right signed DE for B bits ||style="color:DarkGrey;"| BSRA
|-
|<code> <code>BSRL DE,B</code> </code>|| <code>ED 2A</code> || 8 || Shift right DE for B bits ||style="color:DarkGrey;"| BSRL
|-
|<code> <code>BSRF DE,B</code> </code>|| <code>ED 2B</code> || 8 || Shift right DE, filling 1 for B bits ||style="color:DarkGrey;"| BSRF
|-
|<code> <code>BRLC DE,B</code> </code>|| <code>ED 2C</code> || 8 || Rotate left DE for B bits ||style="color:DarkGrey;"| BRLC
|-
|<code> <code>MUL D,E</code> </code>|| <code>ED 30</code> || 8 || Multiply D with E, result in DE ||style="color:DarkGrey;"| MUL
|-
|<code> <code>ADD HL,A</code> </code>|| <code>ED 31</code> || 8 || Add unsigned A to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,A</code> </code>|| <code>ED 32</code> || 8 || Add unsigned A to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,A</code> </code>|| <code>ED 33</code> || 8 || Add unsigned A to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD HL,$im16</code> </code>|| <code>ED 34 low high</code> || 16 || Add a constant to HL ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD DE,$im16</code> </code>|| <code>ED 35 low high</code> || 16 || Add a constant to DE ||style="color:DarkGrey;"| ADD
|-
|<code> <code>ADD BC,$im16</code> </code>|| <code>ED 36 low high</code> || 16 || Add a constant to BC ||style="color:DarkGrey;"| ADD
|-
|<code> <code>PUSH $im16</code> </code>|| <code>ED 8A high low</code> || 23 || Push a constant ||style="color:DarkGrey;"| PUSH
|-
|<code> <code>OUTINB</code> </code>|| <code>ED 90</code> || 16 || OUTI, but don't change B || OTIB
|-
|<code> <code>NEXTREG $im8,$im8</code> </code>|| <code>ED 91 register value</code> || 20 || Write v to Next register r || NREG
|-
|<code> <code>NEXTREG $im8,A</code> </code>|| <code>ED 92 register</code> || 17 || Write A to Next register r || NREG
|-
|<code> <code>PIXELDN</code> </code>|| <code>ED 93</code> || 8 || HL as a pixel address moved one line down || PXDN
|-
|<code> <code>PIXELAD</code> </code>|| <code>ED 94</code> || 8 || HL := as ULA pixel address from D==Y E==X || PXAD
|-
|<code> <code>SETAE</code> </code>|| <code>ED 95</code> || 8 || Get A as a mask for ULA pixel from E || STAE
|-
|<code> <code>JP (C)</code> </code>|| <code>ED 98</code> || 13 || IN (C) then jump to a 64 byte section ||style="color:DarkGrey;"| JP
|-
|<code> <code>LDIX</code> </code>|| <code>ED A4</code> || 16 || Extended LDI byte copy ||style="color:DarkGrey;"| LDIX
|-
|<code> <code>LDWS</code> </code>|| <code>ED A5</code> || 14 || Byte copy as for Layer 2 ||style="color:DarkGrey;"| LDWS
|-
|<code> <code>LDDX</code> </code>|| <code>ED AC</code> || 16 || Extended LDD byte copy ||style="color:DarkGrey;"| LDDX
|-
|<code> <code>LDIRX</code> </code>|| <code>ED B4</code> || 21/16 || Extended LDIR || LIRX
|-
|<code> <code>LDPIRX</code> </code>|| <code>ED B7</code> || 21/16 || Byte copy as for a pattern fill || LPRX
|-
|<code> <code>LDDRX</code> </code>|| <code>ED BC</code> || 21/16 || Extended LDDR || LDRX
|}

More details and the explanations of all Z80 instructions implemented in the Next Z80 CPU follow.

Notes:

* The encoding of the operand of the <code>PUSH $im16</code> is unique: it is the only operand encoded as big-endian.
* The timings (T-States) are based on some limited testing and may not be accurate.
* The shorter aliases of the official mnemonics (the 4-letter column) are those suggested in an initiative led by Matt Davies, the author of Odin assembler, editor and debugger tool for ZX Next.
* A relevant early source for this table could be [https://github.com/z88dk/z88dk/issues/312#issuecomment-322659205 a Christmas 2018 edit of a comment in a discussion of an issue 312 of z88dk].

=== Notation ===
* In the descriptions ''any 8-bit register'' means A, B, C, D, E, H, and L. The registers named F, I and R aren't a part of this set even if they are technically 8 bit registers. Additionally, IXH, IXL, IYH, IYL, which are the high and low byte parts of IX and IY, can be used in some of the instructions as 8-bit registers although this wasn't documented for the original Z80.
* IXY means IX or IY.
* For the status field:
** S means Standard. It's in the Z80 manual. Everything should support it.
** U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
** E means Extension. It ''only'' works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
* Each of the flag effects is documented as follows:
** - means the flag is unchanged.
** 1 or 0 mean the flag is set or reset as appropriate.
** ? means we don't know what effect the instruction has on the flag.
** ! means the instruction has an unusual effect on the flag which is documented in the description.
** S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
** P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it checks BC as loop counter for some of the block copy and search instructions: P/V = (BC != 0)

=== Register and Data manipulation ===
;LD (LoaD)

{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LD r, r' </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||r := r'
|-
|<code>LD r,n </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||7 ||r := n
|-
|<code>LD r, (HL) </code>||Register ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||r := HL*
|-
|<code>LD r, (IXY+d) </code>||Register ||Indexed ||S ||- ||- ||- ||- ||- ||- ||19 ||r := (IXY+d)*
|-
|<code>LD (HL),r </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||7 ||HL* := r
|-
|<code>LD (IXY+d),r </code>||Indexed ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+D)* := r
|-
|<code>LD (HL), n </code>||Indirect ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||HL* := n
|-
|<code>LD (IXY+d), n </code>||Indexed ||Immediate ||S ||- ||- ||- ||- ||- ||- ||19 ||(IXY+d)* := n
|-
|<code>LD A, (BC/DE) </code>||Accumulator ||Indirect ||S ||- ||- ||- ||- ||- ||- ||7 ||A := rr*
|-
|<code>LD A, (nn) </code>||Accumulator ||Address ||S ||- ||- ||- ||- ||- ||- ||13 ||A := (nn)*
|-
|<code>LD (BC/DE), A </code>||Indirect ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||7 ||rr* := A
|-
|<code>LD (nn), A </code>||Address ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||13 ||(nn)* := A
|-
|<code>LD A, I </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := I; P/V:=IFF2
|-
|<code>LD A, R </code>||Accumulator ||Register ||S ||- ||0 ||! ||0 ||S ||S ||9 ||A := R; P/V:=IFF2
|-
|<code>LD I, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||I := A
|-
|<code>LD R, A </code>||Register ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||9 ||R := A
|-
|<code>LD BC/DE/HL/SP, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||10 ||rr := nn
|-
|<code>LD IXY, nn </code>||Register ||Immediate ||S ||- ||- ||- ||- ||- ||- ||14 ||rr := nn
|-
|<code>LD HL, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||16 ||HL := (nn)*
|-
|<code>LD BC/DE/SP/IXY, (nn) </code>||Register ||Address ||S ||- ||- ||- ||- ||- ||- ||20 ||rr := (nn)*
|-
|<code>LD (nn), HL </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||16 ||(nn)* := HL
|-
|<code>LD (nn), BC/DE/SP/IXY </code>||Address ||Register ||S ||- ||- ||- ||- ||- ||- ||20 ||(nn)* := rr
|-
|<code>LD SP, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||6 ||SP := HL
|-
|<code>LD SP, IXY </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||10 ||SP := IXY
|}
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
:* Any 8-bit register can be:
:** loaded with an immediate value;
:** loaded with the contents of any other 8-bit register except I and R;
:** loaded with the contents of, or stored in, memory pointed to by HL;
:** loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
:* Additionally, the accumulator A (only) can be:
:** loaded with the contents of, or stored in, memory pointed to by BC or DE;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address;
:** loaded with the contents of I or R.
:* Any 16-bit register pair can be:
:** loaded with an immediate value;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address.
:* Additionally, SP (only) can be:
:** loaded with the contents of HL, IX, or IY.
:** The planned '''ld hl, sp''' didn't make it to Next yet, one possible workaround is: '''ld hl,0'''; '''add hl,sp''';
:* Memory referred to by HL or through IX can be assigned immediate values.
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
:LD instructions do not alter any flags unless I or R are loaded into A.

;EX (EXchange)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EX DE, HL </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(DE,HL)
|-
|<code>EX AF, AF' </code>||Register ||Register ||S ||! ||! ||! ||! ||! ||! ||4 ||swap(AF,AF')
|-
|<code>EX (SP), HL </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||19 ||swap(SP*,HL)
|-
|<code>EX (SP), IXY </code>||Indirect ||Register ||S ||- ||- ||- ||- ||- ||- ||23 ||swap(SP*,IXY)
|}
:Exchanges the contents of two sources. The only permitted combinations are
:* Exchanging DE and HL;
:* Exchanging AF and AF';
:* Exchanging HL, IX, or IY with the contents of memory pointed to by SP.

;EXX (EXchange all)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EXX </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||swap(BC,BC');swap(DE,DE');swap(HL,HL')
|}
:Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.

;PUSH
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PUSH BC/DE/HL/AF </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||SP-=2; SP*:=rr
|-
|<code>PUSH IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||15 ||SP-=2; SP*:=rr
|-
|<code>PUSH nn </code>||Immediate ||- ||E ||- ||- ||- ||- ||- ||- ||23 ||SP-=2; SP*:=nn
}}

|}
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.

;POP
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>POP BC/DE/HL </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr:=SP*; SP+=2
|-
|<code>POP AF </code>||Register ||- ||S ||! ||! ||! ||! ||! ||! ||10 ||rr:=SP*; SP+=2
|-
|<code>POP IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||rr:=SP*; SP+=2
|}
:Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.
:Popping into AF does set value of flag register F directly to low 8 bits of value from stack.

=== Block Copy ===
;LDI (LoaD and Increment)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDI </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE++; HL++; BC--
|}
:Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;LDIR (LoaD and Increment Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIR </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||21x+16 ||do LDI while(BC>0)
|}
:Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).
:Flag effects are the same as LDI except that P/V will always be reset, because BC by definition reaches 0 before this instruction ends (normally - unless something overwrites LDIR opcode while BC>0).
:Interrupts may interrupt LDIR instruction while looping (after each single LDI sub-part finished) and LDIR will resume after and finish loop properly.

;LDD (LoaD and Decrement)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDD </code>||- ||- ||S ||- ||0 ||L ||0 ||- ||- ||16 ||DE*:=HL*; DE--; HL--; BC--
|}
:Same as LDI, but subtracts 1 from DE and HL instead of adding.

;LDDR (LoaD and Decrement Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDDR </code>||- ||- ||S ||- ||0 ||0 ||0 ||- ||- ||21x+16 ||do LDD while(BC>0)
|}
:Same as LDIR but loops LDD instead of LDI.

;LDWS
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDWS </code>||- ||- ||E ||- ||0 ||! ||S ||S ||S ||14 ||DE*:=HL*; INC L; INC D;
|}
:Next-only extended opcode. Copies the byte pointed to by HL to the address pointed to by DE and increments only L and D. This is used for vertically copying bytes to the Layer 2 display.
:The flags are identical to what the '''INC D''' instruction would produce.
:Note the source data are read only from single 256B (aligned) block of memory, because only L is incremented, not HL.

;LDIX, LDIRX, LDDX, LDDRX
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDIX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL++; BC--
|-
|<code>LDIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDIX while(BC>0)
|-
|<code>LDDX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||16 ||{if HL*!=A DE*:=HL*;} DE++; HL--; BC--
|-
|<code>LDDRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do LDDX while(BC>0)
|}
:Next-only extended opcodes. Behave similarly as their non-X equivalents except the byte is not copied if it is equal to A and LDDX/LDDRX advance DE by incrementing it (like LDI), while HL is decremented (like LDD).
:Second difference to non-X instructions (as usual with next-only opcodes due to implementation), the extended ones don't modify any flags.

;LDPIRX
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>LDPIRX </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||21/16 ||do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
|}
:Similar to LDIRX except the source byte address is not just HL, but is obtained by using the top 13 bits of HL and the lower 3 bits of DE and HL does not increment during whole loop (HL works as base address of aligned 8 byte lookup table, DE works as destination and also wrapping index 0..7 into table). This is intended for "pattern fill" functionality.

=== Block Search ===
;CPI (ComPare and Increment)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPI </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL++; BC--
|}
:Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

;CPIR (ComPare and Increment Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPIR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPI while (!Z && BC>0)
|}
:Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0).
:Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.

;CPD (ComPare and Decrement)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPD </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||16 ||HL*==A?; HL--; BC--
|}
:Same as CPI, but subtracts 1 from HL instead of adding it.

;CPDR (ComPare and Decrement Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPDR </code>||- ||- ||S ||- ||1 ||L ||S ||! ||S ||21x+16 ||do CPD while (!Z && BC>0)
|}
:Same as CPIR but loops CPD instead of CPI.

=== Arithmetic ===
;ADD
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADD A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r
|-
|<code>ADD A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n
|-
|<code>ADD A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*
|-
|<code>ADD A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*
|-
|<code>ADD HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||11 ||HL+=rr
|-
|<code>ADD IXY, BC/DE/IXY/SP </code>||Register ||Register ||S ||S ||0 ||- ||! ||- ||- ||15 ||IXY+=rr
|-
|<code>ADD HL/DE/BC, A </code>||Register ||Register ||E ||? ||- ||- ||- ||- ||- ||8 ||rr+=unsigned A
|-
|<code>ADD HL/DE/BC, nn </code>||Register ||Immediate ||E ||- ||- ||- ||- ||- ||- ||16 ||rr+=nn
|}
:Adds values together. Legal combinations are:
:* When adding 8-bit values the first parameter must be A and the second may be:
:** The contents of an 8-bit register;
:** An immediate value;
:** The contents of memory pointed to by HL or by indexing based on IX or IY.
:* When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register.
:* For 16 bit additions (regular Z80), H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)
:* On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A (A will be zero extended to 16 bits) or an 16bit immediate value.

;ADC (ADd with Carry)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>ADC A, r </code>||Accumulator ||Register ||S ||S ||0 ||V ||S ||S ||S ||4 ||A+=r+(CF?1:0)
|-
|<code>ADC A, n </code>||Accumulator ||Immediate ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=n+(CF?1:0)
|-
|<code>ADC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||0 ||V ||S ||S ||S ||7 ||A+=HL*+(CF?1:0)
|-
|<code>ADC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||0 ||V ||S ||S ||S ||19 ||A+=(IXY+d)*+(CF?1:0)
|-
|<code>ADC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||0 ||V ||! ||S ||S ||15 ||HL+=rr+(CF?1:0)
|}
:Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if carry from bit 11; otherwise, it is reset.

;SUB
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SUB r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A -= r
|-
|<code>SUB n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= n
|-
|<code>SUB (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A -= HL*
|-
|<code>SUB (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A -= (IXY+d)*
|}
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.

;SBC (SuBtract with Carry, er, borrow)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SBC A, r </code>||Accumulator ||Register ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=(r+(CF?1:0))
|-
|<code>SBC A, n </code>||Accumulator ||Immediate ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(n+(CF?1:0))
|-
|<code>SBC A, (HL) </code>||Accumulator ||Indirect ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=(HL*+(CF?1:0))
|-
|<code>SBC A, (IXY+d) </code>||Accumulator ||Indexed ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=((IXY+d)+(CF?1:0))
|-
|<code>SBC HL, BC/DE/HL/SP </code>||Register ||Register ||S ||S ||1 ||V ||! ||S ||S ||15 ||HL-=(rr+(CF?1:0))
|}
:Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset.

;AND, OR, XOR
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>AND r </code>||Register ||- ||S ||0 ||0 ||P ||1 ||S ||S ||4 ||A := A & r
|-
|<code>AND n </code>||Immediate ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & n
|-
|<code>AND (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||1 ||S ||S ||7 ||A := A & HL*
|-
|<code>AND (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||1 ||S ||S ||19 ||A := A & (IXY+d)*
|-
|<code>OR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A OR r
|-
|<code>OR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR n
|-
|<code>OR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A OR HL*
|-
|<code>OR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A OR (IXY+d)*
|-
|<code>XOR r </code>||Register ||- ||S ||0 ||0 ||P ||0 ||S ||S ||4 ||A := A ^ r
|-
|<code>XOR n </code>||Immediate ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ n
|-
|<code>XOR (HL) </code>||Indirect ||- ||S ||0 ||0 ||P ||0 ||S ||S ||7 ||A := A ^ HL*
|-
|<code>XOR (IXY+d) </code>||Indexed ||- ||S ||0 ||0 ||P ||0 ||S ||S ||19 ||A := A ^ (IXY+d)*
|}
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.

:XOR A is faster and shorter than LD A,0

;MIRROR
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MIRROR A </code>||Register ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A[76543210]:=A[01234567]
|}
:Next extended opcode. Mirrors (reverses the order) of bits in the accumulator. Older core versions supported MIRROR DE, but this was removed.

;CP (ComPare)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CP r </code>||Register ||- ||S ||S ||1 ||V ||S ||S ||S ||4 ||A-=r?
|-
|<code>CP n </code>||Immediate ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=n?
|-
|<code>CP (HL) </code>||Indirect ||- ||S ||S ||1 ||V ||S ||S ||S ||7 ||A-=HL*?
|-
|<code>CP (IXY+d) </code>||Indexed ||- ||S ||S ||1 ||V ||S ||S ||S ||19 ||A-=(IXY+d)?
|}
:Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
:* CP is ''not'' equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.

;TEST
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>TEST n </code>||Immediate ||- ||E ||S ||? ||P ||S ||S ||S ||11 ||A&n?
|}
: Next extended opcode. Similar to CP, but performs an AND instead of a subtraction.

;INC (INCrement)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INC r </code>||Register ||- ||S ||- ||0 ||! ||S ||S ||S ||4 ||r++
|-
|<code>INC (HL) </code>||Indirect ||- ||S ||- ||0 ||! ||S ||S ||S ||11 ||HL*++
|-
|<code>INC (IXY+d) </code>||Indexed ||- ||S ||- ||0 ||! ||S ||S ||S ||23 ||(IXY+d)*++
|-
|<code>INC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr++
|-
|<code>INC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr++
|}
:Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
:* INC A is faster than ADD 1.

;DEC (DECrement)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DEC r </code>||Register ||- ||S ||- ||1 ||! ||S ||S ||S ||4 ||r--
|-
|<code>DEC (HL) </code>||Indirect ||- ||S ||- ||1 ||! ||S ||S ||S ||11 ||HL*--
|-
|<code>DEC (IXY+d) </code>||Indexed ||- ||S ||- ||1 ||! ||S ||S ||S ||23 ||(IXY+D)*--
|-
|<code>DEC BC/DE/HL/SP </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||6 ||rr--
|-
|<code>DEC IXY </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||rr--
|}
:Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
:* DEC A is faster than SUB 1.

;RLC (Rotate Left Circular)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=x; CF:=x
|-
|<code>RLC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=x; CF:=x
|-
|<code>RLC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=x; CF:=x
|-
|<code>RLC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=x; CF:=x; r:=(IX+d)*
|}
:Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.

;RL (Rotate Left)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x
|-
|<code>RL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=CF; CF:=x
|-
|<code>RL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=CF; CF:=x
|-
|<code>RL r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=CF; CF:=x; r:=(IX+d)*
|}
:Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.

;RRC, RR (Rotate Right Circular, Rotate Right)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRC r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=x; CF:=x
|-
|<code>RRC (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=x; CF:=x
|-
|<code>RRC (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=x; CF:=x
|-
|<code>RRC r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=x; CF:=x; r:=(IX+d)*
|-
|<code>RR r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x
|-
|<code>RR (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=CF; CF:=x
|-
|<code>RR (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=CF; CF:=x
|-
|<code>RR r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=CF; CF:=x; r=(IX+d)*
|}
:Same as RLC and RL except they rotate right instead of left.

;SLA (Shift Left Arithmetic)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SLA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r<<1
|-
|<code>SLA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*<<1
|-
|<code>SLA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*<<1
|-
|<code>SLA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*<<1; r=(IX+d)*
|}
:Same as RL except bit 0 is set to zero, not the previous contents of Carry.

;SRA (Shift Right Arithmetic)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRA r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||S ||8 ||r:=r>>1 OR r[7]
|-
|<code>SRA (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=HL*>>1 OR HL*[7]
|-
|<code>SRA (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=(IXY+d)*>>1 OR (IXY+d)*[7]
|-
|<code>SRA r,(IX+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IX+d)*:=(IX+d)*>>1 OR (IX+d)*[7]; r:=(IX+d)*
|}
:Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry.

;SRL (Shift Right Logical)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SRL r </code>||Register ||- ||S ||! ||0 ||P ||0 ||S ||0 ||8 ||r:=unsigned(r)>>1
|-
|<code>SRL (HL) </code>||Indirect ||- ||S ||! ||0 ||P ||0 ||S ||0 ||15 ||HL*:=unsigned(HL*)>>1
|-
|<code>SRL (IXY+d) </code>||Indexed ||- ||S ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1
|-
|<code>SRL r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||0 ||23 ||(IXY+d)*:=unsigned((IXY+d)*)>>1; r:=(IXY+d)*
|}
:Same as SLA except it shifts right instead of left.

;RLCA, RLA, RRCA, RRA
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=x; CF:=x
|-
|<code>RLA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x
|-
|<code>RRCA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=x; CF:=x
|-
|<code>RRA </code>||- ||- ||S ||! ||0 ||- ||0 ||- ||- ||4 ||x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x
|}
:Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.

;SLL (Shift Left Logical)
:This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.

;SL1 or SLI (Shift Left and Add 1) or (Shift Left and Increment)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SL1 r </code>||Register ||- ||U ||! ||0 ||P ||0 ||S ||S ||8 ||r:=(r<<1)+1
|-
|<code>SL1 (HL) </code>||Indirect ||- ||U ||! ||0 ||P ||0 ||S ||S ||15 ||HL*:=(HL*<<1)+1
|-
|<code>SL1 (IXY+d) </code>||Indexed ||- ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1
|-
|<code>SL1 r,(IXY+d) </code>||Register ||Indexed ||U ||! ||0 ||P ||0 ||S ||S ||23 ||(IXY+d)*:=((IXY+d)*<<1)+1; r=(IXY+d)*
|}
:Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.

;RLD (Rotate Left bcd Digit)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RLD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]
|}
:Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.

;RRD (Rotate Right bcd Digit)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RRD </code>||- ||- ||S ||- ||0 ||P ||0 ||S ||S ||18 ||x=HL*; HL*[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]
|}
:Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.

;Barrel (variable amount) shift and rotate (cores v2+ only)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BSLA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&31) ||8
|-
|<code>BSRA DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=signed(DE)>>(B&31) ||8
|-
|<code>BSRL DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=unsigned(DE)>>(B&31) ||8
|-
|<code>BSRF DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=~(unsigned(~DE)>>(B&31)) ||8
|-
|<code>BRLC DE,B </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||DE:=DE<<(B&15) OR DE>>(16-B&15) ||8
|}
:Shift instructions use only bits 4..0 of B, BSLA shifts DE left, BSRA/BSRL/BSRF shifts DE right in arithmetic/logical/fill-one way. BRLC rotates DE left by B places, uses only bits 3..0 of B (to rotate right, use B=16-places).

If you are implementing BSRF in C (or similar), be careful with implicit variable type promotion. You will need to do something like this: DE:=~((uint16_t)~DE>>(B&31))

;CPL (ComPLement)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CPL </code>||- ||- ||S ||- ||1 ||- ||1 ||- ||- ||4 ||A:=~A
|}
:Inverts the contents of the accumulator.

;NEG (NEGate)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEG </code>||- ||- ||S ||! ||1 ||! ||S ||S ||S ||8 ||A:=0-A
|}
:Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.

;CCF (Complement Carry Flag)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CCF </code>||- ||- ||S ||! ||0 ||- ||! ||- ||- ||4 ||CF:=!CF
|}
:Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.

;SCF (Set Carry Flag)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SCF </code>||- ||- ||S ||1 ||0 ||- ||0 ||- ||- ||4 ||CF:=1
|}
:Sets the carry flag.

;BIT (test BIT)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>BIT b,r </code>||Immediate ||Register ||S ||- ||0 ||? ||1 ||! ||? ||8 ||r[b]==1?
|-
|<code>BIT b,(HL) </code>||Immediate ||Indirect ||S ||- ||0 ||? ||1 ||! ||? ||12 ||HL*[b]==1?
|-
|<code>BIT b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||0 ||? ||1 ||! ||? ||20 ||(IXY+d)*[b]==1?
|}
:Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.

;SET (SET bit)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SET b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r OR (1<<b)
|-
|<code>SET b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* OR (1<<b)
|-
|<code>SET b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* OR (1<<b)
|-
|<code>SET r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* OR (1<<b); r:=(IX+d)*
|-
|<code>SETAE </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=unsigned($80)>>(E&7)
|}
:Sets the numbered bit on target value. The possible targets are the same as BIT. The three parameter variant is undocumented and stores the result in a register as well as performing the SET.
:SETAE is a Next extended opcode which takes the bit number to set from E (only the low 3 bits) and sets whole A to value of that bit, but counted from top to bottom (E=0 will produce A:=$80, E=7 will produce A:=$01). This works as pixel mask for ULA bitmap modes, when E is 0..255 x-coordinate.

;RES (RESet bit)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RES b,r </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||8 ||r:=r & (~(1<<b))
|-
|<code>RES b,(HL) </code>||Immediate ||Register ||S ||- ||- ||- ||- ||- ||- ||15 ||HL*:=HL* & (~(1<<b))
|-
|<code>RES b,(IXY+d) </code>||Immediate ||Indexed ||S ||- ||- ||- ||- ||- ||- ||23 ||(IXY+d)*:=(IXY+d)* & (~(1<<b))
|-
|<code>RES r,b,(IX+d) </code>||Immediate ||Indexed ||U ||- ||- ||- ||- ||- ||- ||23 ||(IX+d)*:=(IX+d)* & (~(1<<b)); r:=(IX+d)*
|}
:Resets the numbered bit on target value. The possible targets are the same as BIT.

;DAA (Decimal Adjust Accumulator)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DAA </code>||- ||- ||S ||! ||- ||P ||! ||S ||S ||8 ||if(A&$0F>$09 or HF) A±=$06; if(A&$F0>$90 or CF) A±=$60 (± depends on NF)
|}
:Modifies the contents of the accumulator based on the flags left by previous operation to correct for binary coded decimal (BCD).

;MUL (MULtiply)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>MUL d,e </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||DE:=D*E
|}
:Next extended opcode. Multiplies D by E, storing 16 bit result into DE. Does not alter any flags (the opcode is not compatible with any of the R800/Z180/eZ80/... variants of MUL, it is solely Next specific).

;SWAPNIB (SWAP NIBbles)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>SWAPNIB </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||A:=A[3210]<<4 OR A[7654]>>4
|}
:Next extended opcode. Swaps the high and low nibbles of the accumulator.

;PIXELAD (PIXEL ADdress)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELAD </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
|}
:Next extended opcode. Takes E and D as the X,Y coordinate of a point and calculates the address of the byte containing this pixel in the pixel area of standard ULA screen 0, storing it in HL.

;PIXELDN (PIXEL DowN)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>PIXELDN </code>||- ||- ||E ||- ||- ||- ||- ||- ||- ||8 ||if(HL&$0700!=$0700) HL+=256; 
else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; 
else HL:=HL&$F81F+$0800
|}
:Updates the address in HL to move down by one line of pixels.

=== Control Flow ===
;JP (JumP)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=nn
|-
|<code>JP (HL) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC:=HL (not PC:=HL*)
|-
|<code>JP (IXY) </code>||Register ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||PC:=IXY (not PC:=IXY*)
|-
|<code>JP (C) </code>||Register ||- ||E ||? ||? ||? ||? ||? ||? ||13 ||PC:=PC&$C000+IN(C)<<6
|}
:Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs ''look'' like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to. The JP (C) sets bottom 14 bits of current PC* to value read from I/O port: PC[13:0] = (IN (C) << 6) (can be used to execute code block read from a disk stream) * "current PC" is address of next instruction after JP (C), as the PC is advanced by fetching op code from memory and is already advanced when execution happens - if the JP instruction resides at the very end of 16k memory block (..FE or ..FF address), then newly composed PC value will land into following 16k block.

;JP cc (JumP conditionally)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JP Z/NZ/NC/C/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||if cc PC:=nn
|}
:Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.

;JR (Jump Relative)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>JR nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ||PC+=nn
|-
|<code>JR C/NC/Z/NZ, nn </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||12 ; 7 if not cc ||if cc PC+=nn
|}
:Jumps to an alternate address by ''adding'' the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.

;DJNZ (Decrement reg. b and Jump if Not Zero)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DJNZ n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||13 ||B--; if B!=0 PC+=nn
|}
:Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.

;CALL
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>CALL nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ||SP-=2; SP*:=PC; PC:=nn
|-
|<code>CALL Z/NZ/C/NC/PO/PE/P/M, nn </code>||Address ||- ||S ||- ||- ||- ||- ||- ||- ||17 ; 10 if not cc ||if cc {SP-=2; SP*:=PC; PC:=nn}
|}
:Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.
:* If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)

;RET (RETurn)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RET </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||10 ||PC:=SP*; SP+=2
|-
|<code>RET Z/NZ/C/NC/PO/PE/P/M </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||11 ; 5 if not cc ||if cc {PC:=SP*; SP+=2}
|}
:POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.

;RETI (RETurn from Interrupt)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||PC:=SP*; SP+=2
|}
:Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).

;RETN (RETurn from Non-maskable interrupt)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RETN </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||14 ||IFF1:=IFF2; PC:=SP*; SP+=2
|}
:Returns from a non-maskable interrupt service routine.

;RST (ReSTart)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>RST n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||11 ||CALL n
|}
:Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.

;NOP (No OPeration)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NOP </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||PC+=1
|}
:Does "nothing" (just usual housekeeping like refreshing memory and advancing program counter to next instruction).

;HALT
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>HALT </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||waits for interrupt
|}
:Suspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.

;DI (Disable Interrupts)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>DI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=0; IFF2:=0
|}
:Disables maskable interrupts.

;EI (Enable Interrupts)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>EI </code>||- ||- ||S ||- ||- ||- ||- ||- ||- ||4 ||IFF1:=1; IFF2:=1
|}
:Enables maskable interrupts (after next instruction, i.e. for example "EI RET" - the interrupt may happen only after RET instruction is finished (or "EI DI" pair of instructions will not allow any maskable interrupt to happen).

;IM (Interrupt Mode)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IM n </code>||Immediate ||- ||S ||- ||- ||- ||- ||- ||- ||8 ||Interrupt mode:=n
|}
:Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)

=== Input and Output ===
;IN r, (c); OUT (c), r
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN r, (c) </code>||Register ||Register ||S ||- ||0 ||P ||0 ||S ||S ||12 ||r := in(BC)
|-
|<code>OUT (c),r </code>||Register ||Register ||S ||- ||- ||- ||- ||- ||- ||12 ||out(BC,r)
|}
:Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.

;IN (c); OUT (c), 0
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN (c) </code>||Register ||- ||U ||- ||0 ||P ||0 ||S ||S ||12 ||in(BC)?
|-
|<code>OUT (c),0 </code>||Register ||Immediate ||U ||- ||- ||- ||- ||- ||- ||12 ||out(BC,0)
|}
:Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode. The Next FPGA does output zero, but some Z80 chips manufactured differently from early batches output different value like 255, so it is not recommended to use OUT (C),0 if you want to reuse your code also on classic ZX Spectrum or publish it as example.

;IN a, (n); OUT (n), a
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IN A, (n) </code>||Accumulator ||Immediate ||S ||- ||- ||- ||- ||- ||- ||11 ||A := in(An)
|-
|<code>OUT (n),A </code>||Immediate ||Accumulator ||S ||- ||- ||- ||- ||- ||- ||11 ||out(An,A)
|}
:Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.

;INI (INput and Increment)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL++; B--
|}
:Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; C, S, H, and P/V are destroyed.

;INIR (INput and Increment Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>INIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do INI while(B>0)
|}
:Loops INIR until B reaches 0, so that if INIR starts with B=0 it loops 256 times. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

;IND, INDR (INput and Decrement, INput and Decrement Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>IND </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||HL*:=in(BC); HL--; B--
|-
|<code>INDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do IND while(B>0)
|}
:Behave like INI and INIR except that HL is decremented instead of incremented.

;OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTI </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL++
|-
|<code>OTIR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTI while (B>0)
|-
|<code>OUTD </code>||- ||- ||S ||? ||1 ||? ||? ||! ||? ||16 ||B--; out(BC,HL*); HL--
|-
|<code>OTDR </code>||- ||- ||S ||? ||1 ||? ||? ||1 ||? ||21x+16 ||do OUTD while (B>0)
|}
:Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented '''before''' the output instead of after. Condition check on B is performed '''after''', so that if OTIR starts with B=0 it loops 256 times.

;OUTINB (Out and Increment with No B)
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>OUTINB </code>||- ||- ||E ||? ||? ||? ||? ||? ||? ||16 ||out(BC,HL*); HL++
|}
:Next extended opcode. Behaves like OUTI, but doesn't decrement B.

;NEXTREG
{| class="wikitable" style="margin:auto"
!Mnemonic || Addressing mode 1 || Addressing mode 2 || Status || C || N || PV || H || Z || S || Tstates || Shortfx
|-
|<code>NEXTREG n,n' </code>||Immediate ||Immediate ||E ||- ||- ||- ||- ||- ||- ||20 ||HwNextReg_n:=n'
|-
|<code>NEXTREG n, A </code>||Immediate ||Accumulator ||E ||- ||- ||- ||- ||- ||- ||17 ||HwNextReg_n:=A
|}
:Next extended opcode. Directly sets the [[Board feature control|Next Feature Control Registers]] without going through ports {{PortNo|$243B}} and {{PortNo|$253B}}.

=== A note on some Z80-N specific observations ===
2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.

2025-01-25: Testing 3.02.x 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

=== Errata ===

This section lists the changes of the specification of the behavior of Z80N instructions, compared to the previous content of this wiki page.

2022-01-11: The previous versions of this page didn't match what was [http://www.z80.info/zip/z80-documented.pdf documented] for several years, that regular Z80 INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR instructions do modify carry flag (contrary to the official Z80 documentation and many Internet resources describing Z80 instructions).

File Formats

2025-09-08T10:05:42Z

Sol HSA: loadable directory

== Supported File Formats in NextZXOS ==

NextZXOS can directly read and load the following file types: `.bas`, `.tap`, `.z80`, `.sna`, `.snx`, `.dot`, `.o`, `.p`. Many other file types are supported via external dot commands.

{| class="wikitable sortable"
! File Extension !! Description !! Notes
|-
| .z80 || Spectrum snapshot file || More suitable for emulator compatibility than real hardware. Loadable via NextZXOS browser, SPECTRUM keyword, esxDOS NMI menu, and exDOS `.snapload` command.
|-
| .sna || Spectrum snapshot file || Supports 48K and 128K. Loadable via browser, SPECTRUM keyword, esxDOS NMI, and `.snapload`. Private data appended is ignored by NextZXOS but prevents loading via esxDOS. NextZXOS reconfigures system based on file type.
|-
| .snx || Spectrum snapshot file || Identical to 128K .sna, but leaves file handle 0 open. Program must close it. May contain private data. Not supported by esxDOS.
|-
| .o || ZX80 snapshot || —
|-
| .p || ZX81 snapshot || —
|-
| [[NEX_file_format|.nex]] || Next executable file || Takes over machine. Can coexist with NextZXOS if careful. Loadable via browser and `.nexload`. CSpect emulator supports loading. Not supported by esxDOS.
|-
| .dot || Dot command format || For programs that coexist with BASIC/NextZXOS and return safely.
|-
| .tap || Tape container format || Holds many files, emulator-compatible. Browser prompts for load mode: standard, USR0, or 48K.
|-
| .bas || BASIC program || Native SD card format for BASIC programs. First 128 bytes are standard +3DOS header.
|-
| .run || Loadable Directory || If a directory ends with .run and contains run.bas, browser runs the bas when directory is selected.
|-
| .scr || Standard Spectrum screenshot || 256x192, 15 colours, 2 per cell. Headered files (7,040 bytes) or headerless (6,912 bytes). Both are supported.
|-
| .shc || Timex 8x1 Hi-colour screenshot || 256x192, 15 colours.
|-
| .shr || Timex Hi-res screenshot || 512x192, mono.
|-
| .slr || Low-res screenshot || 128x96, 256 colours.
|-
| .sl2 || Layer 2 screenshot || 256x192, 256 colours. 128-byte +3DOS header + 49,152 bytes of pixel data. No palette data.
|-
| .pal || 9-bit palette format || 256 pairs of bytes in %RRRGGGBB, %P000000B format. Priority bit (P) causes pixel layering. Loadable via Screenshots menu (M1 or F9).
|-
| .npl || Extended palette format || First 512 bytes identical to .pal. Byte 513 is transparency index or mask. Created and loaded via WASPtools.
|-
| .nxi || Layer 2 screen format || 49,152 bytes = screen data. 49,664 bytes = screen + palette. Used by PLOTIT, Dnext, zxnext_bmp_tools, and Jim Bagley’s tools.
|-
| .vid || [[VID file format|Video format]] || Played via `.playvid`. Formats supported:
* 320x240 @ 16.7fps, 15.6kHz
* 256x240 @ 16.7fps, 31.1kHz
* 256x192 @ 25fps, 23kHz
A tool for converting video files to .vid can be found here https://github.com/em00k/MakeVid-Release
|}

=== Special Notes ===
* The `.tzx` format is recognised by the browser, but files can only be loaded if a Raspberry Pi is installed in your Next. See the FAQ for details.

Palettes

2025-03-15T14:10:59Z

Sol HSA: added alternative rgb values

To increase the number of available colours on screen, the Spectrum Next supports palletized colours.

Colour IDs in [[Layer 2]], [[Tilemap]] and [[Sprites]] are always taken as palette indices. Colour values in the ULA are mapped to the palette as fixed indices, or can be taken as partial palette indices if Enhanced ULA mode is enabled. The palette entry numbers for standard ULA mode are: 0-7 for the standard ink colors, 8-15 for BRIGHT ink colors, 16-23 for standard paper and border colors, and 24-31 for BRIGHT paper colors.

With Enhanced ULA mode enabled, the {{NextRegNo|$42}} defines how particular ULA attribute breaks into INK and PAPER color. The INK colors are mapped from index 0 in palette, PAPER (and BORDER) colors are mapped from index 128, except when in "full ink" mode (ink mask = 255), then PAPER and BORDER color is taken from {{NextRegNo|$4A}}.

Palette configuration can be done through registers $40-$44 and $6B. {{NextRegNo|$43}} sets which palette is being set up. There are two palettes each for Layer 2, Sprites, Tilemap and ULA; which one of the two is used for each is selected using the lower bits of {{NextRegNo|$43}} and in {{NextRegNo|$6B}}.

Once a palette is selected, {{NextRegNo|$40}} sets the palette entry number to set up; you can then send the color to set it to on {{NextRegNo|$41}} ''or'' {{NextRegNo|$44}} which then auto-increment. $41 is used for sending 8-bit colours in RRRGGGBB format; the "missing" third blue bit is set to an OR between the other two. $44 is used for sending 9-bit colours in two byte packets; the first byte sent should be RRRGGGBB as with $41, and the second byte's LSB fills in the third blue bit. For Layer 2 color the top bit in second byte signals "priority" colour, which makes particular Layer 2 pixel to be drawn on top of everything else, overriding current order of layers.

[[File:256-palette.png|left|thumb| Default 256 colour 8-bit indexed palette.]]
 

Since next has 3 bit color and modern computers have 8 bit, conversion between the two always leads to either inventing or discarding information. Here's an alternative 8-bit palette that is calculated by scaling the 3 bit (0..7) values to 8 bit (0..255) linearly (res=src*255/7):

[[File:256-palette-2.png|thumb|left|Alternate 8 bit rgb values]]

File:256-palette-2.png

2025-03-15T14:07:09Z

Sol HSA:

alternate way to calculate the default 256 color palette for desktop

Refresh Rates

2025-02-20T12:50:58Z

Sol HSA:

This depends on the model, as the video timing is driven by which Spectrum's video timing is currently used. Which one depends on either the personality chosen, or what kind of tape load you do from the NextZXOS browser.

<pre>With VGA or RGB 50 Hz, 1T = 1/3.5MHz
48K = 224T * 312 = 69888T per frame = 50.08Hz
128K = 228T * 311 = 70908T per frame = 49.36Hz
Pentagon = 224T * 320 = 71680T per frame = 48.83Hz</pre>

This is at VGA 0, the perfect timings where the system clock is 28MHz. As you move up through VGA 1 to VGA 6, the system clock is increased according to nextreg [https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/nextreg.txt#L159 0x11]. Then the refresh rate has to be modified.

For example, at VGA 5 the system clock is 32MHz. The spectrum runs at 32/28*3.5MHz = 4MHz in real time, and the refresh rate is 32/28*50.08 = 57.23Hz.

The video mode chosen should always be VGA 0 or RGB at 50Hz. This option of increasing steps VGA 1-6 are for monitors that cannot sync to 50Hz only. All relative timing in the machine is kept the same but the real time speed is higher so programs run faster and sound is higher pitch.

The 60Hz VGA timing should only be used if the monitor can't do anything under 60Hz, or if the higher 50Hz settings are too annoying due to high speed. But all the relative timing relationships are broken, and programs depending on timing will not display properly, just like with HDMI.

If the display can only do 60Hz VGA or the higher 50Hz VGA settings is too annoying, We would honestly recommend looking for another, more capable monitor.

The pixel resolution of the VGA signal is 704 x 568.

See also: https://wiki.specnext.dev/Video_Timing_Register

AY Info

2024-11-03T13:14:18Z

Sol HSA: updated to 78a6ee50

{{Port
|Number=$BFF5
|NumberDec=49141
|PortMask=1011111111110101
|ShortDesc=AY information
|Readable=yes
|Writable=no
}}
bits 7:6 = active AY chip
11 = AY 0 is active
10 = AY 1 is active
01 = AY 2 is active
bit 5 = Reserved
bits 4:0 = currently selected AY register

Turbo Sound Next Control

2024-11-03T13:11:50Z

Sol HSA: updated to 78a6ee50

{{Port
|Number=$FFFD
|NumberDec=65533
|PortMask=%11-- ---- ---- --0-
|ShortDesc=Controls stereo channels and selects active sound chip and sound chip channel.
|Readable=Yes
|Writable=Yes
|Subsystem=Turbo Sound Next
}}
There are three AY chips in the zx next whose selection is made through port 0xFFFD. The currently active AY chip continues
to use port 0xFFFD for register select and port 0xBFFD for data. All AY chips generate stereo sound unless placed in mono
mode per nextreg 0x08 and nextreg 0x09. The Next adds port 0xBFF5 to read information about the currently selected AY chip
and its currently selected register.

When read, returns the value stored in the selected register on the active AY chip

When written to with the top bit set, selects the active sound chip.

{| class="wikitable"
! Bit !! Function
|-
| 7 || Must be 1
|-
| 6 || Enable left audio
|-
| 5 || Enable right audio
|-
| 4-2 || Must be 1
|-
| 1-0 || Select active chip. 0-3: unused, AY3, AY2, AY1.
|}

Otherwise, selects the register number to access from the active sound chip.

Pentagon 1024 paging

2024-11-03T13:07:00Z

Sol HSA: updated to 78a6ee50

{{Port
|Number=$EFF7
|NumberDec=61431
|PortMask=1110111111110111
|ShortDesc=Paging in Pentagon 1024K mode
|Readable=no
|Writable=yes
}}
bit 3 = 1 to overlay the bottom 16K with ram from 16k bank 0
bit 2 = 0 to enable Pentagon 1024 mapping and disable bit 5 port 0x7ffd locking, 1 to select standard zx128 mapping **
* ** Applies only when pentagon 1024 mapping mode is enabled via nextreg 0x8f.

Memory Paging Control

2024-11-03T13:03:33Z

Sol HSA: updated to 78a6ee50

{{Port
|Number=$7FFD
|NumberDec=32765
|PortMask=%01-- ---- ---- --0-
|ShortDesc=Selects active RAM, ROM, and displayed screen.
|Readable=No
|Writable=Yes
|Subsystem=Memory map
}}
Selects the active memory page in slot 4 at $C000. See [[Memory map]] (soft reset = 0).

Any values written to this port should also be stored at $5B5C if any OS routines are in use.

{| class="wikitable"
! Bit !! Effect
|-
| 6-7 || Extra two bits for 16K RAM bank if in Pentagon 512K / 1024K mode (see {{PortNo|$DFFD}}, {{NextRegNo|$8f}})
|-
| 5 || Lock memory paging (setting to 1 locks pages and cannot be unlocked until next reset (on regular ZX128))
|-
| 4 || ROM select (0 = 128k editor, 1 = 48k basic) (low bit of ROM select on +2/+3)
|-
| 3 || Shadow Screen toggle (0 = bank 5, 1 = bank 7) - this is ULA layer shadow, not related to {{NextRegNo|$13}}
|-
| 0-2 || Bank number for slot 4 ($C000)
|}

Since core3.0 the Layer 2 can be used together with shadow ULA screen from Bank 7 (previous cores did disable Layer 2).

When the port is locked (bit 5), the shadow screen toggle is considered part of the paging, i.e. it's not possible to flip between shadow and regular screen. Except for {{NextRegNo|$69}} which works even when port is locked, and you can unlock the port back (without reset) with {{NextRegNo|$08}}.

ULA shadow screen from Bank 7 has higher priority than Timex modes, setting bit 3 to "1" when in one of the extended Timex graphic modes will switch to classic ZX128 ULA mode using Bank 7 data.

Keyboard

2024-11-03T13:00:33Z

Sol HSA: updated to 78a6ee50

{{Port
|Number=$**FE
|NumberDec=254
|PortMask=%xxxx xxxx ---- ---0 where only one bit in x is 0
|ShortDesc=Series of specific ports that read keyboard key presses.
|Readable=Yes
|Writable=No
|Subsystem=Input
}}
bit 6 = EAR in from the tape audio jack
bits 4:0 = key column result from keyboard, active low

* nextreg 0x08 bit 0 can be set to select issue 2 keyboard which will affect reads of bit 6

Reads keys on the keyboard depending on the upper byte of the port number. The five keys are represented by bits 0-4 of the read byte, listed below with bit 4 first down to bit 0. A zero means that the key is pressed.

The top eight bits of the port address are active low signals that select one or more key rows for reading.

{| class="wikitable"
! Port upper byte !! Keys affected (row of keys)
|-
| $7F (bit 7) || B, N, M, Symbol Shift, Space
|-
| $BF (bit 6) || H, J, K, L, Enter
|-
| $DF (bit 5) || Y, U, I, O P
|-
| $EF (bit 4) || 6, 7, 8, 9, 0
|-
| $F7 (bit 3) || 5, 4, 3, 2, 1
|-
| $FB (bit 2) || T, R, E, W, Q
|-
| $FD (bit 1) || G, F, D, S, A
|-
| $FE (bit 0) || V, C, X, Z, Caps Shift
|}

[[File:Speckeys.png]]

=== Wireless Keyboards ===
Most ps/2 keyboards commonly seen today are wired. Two models of wireless keyboard known to work well with the Next are the '''Microsoft Wireless Elite Keyboard 1011''' and the '''Logitech Cordless Desktop Keyboard EX110'''.

XADC D1 Register

2024-11-03T12:52:35Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$F9
|Readable=Yes
|Writable=Yes
|ShortDesc=Issue 4 only
}}
bits 7:0 = MSB data connected to XADC DRP data bus D15:8
DRP reads store result here, DRP writes take value from here

XADC D0 Register

2024-11-03T12:51:40Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$F9
|Readable=Yes
|Writable=Yes
|ShortDesc=Issue 4 only
}}
bits 7:0 = LSB data connected to XADC DRP data bus D7:0
* DRP reads store result here, DRP writes take value from here

XADC Register

2024-11-03T12:50:34Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$F8
|Readable=Yes
|Writable=Yes
|ShortDesc=Issue 4 only
}}
bit 7 = 1 to write to XADC DRP port, 0 to read from XADC DRP port **
bits 6:0 = XADC DRP register address DADDR
* An XADC register read or write is initiated by writing to this register
* There must be at least six 28 MHz cycles after each r/w to this register
* ** Reads as 0

XDEV command

2024-11-03T12:49:15Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$F0
|Readable=Yes
|Writable=Yes
|ShortDesc=Issue 4 only
}}
* Select Mode
(R)
bit 7 = 1 if in select mode
bits 1:0 indicate currently selected device
00 = none
01 = Xilinx DNA
10 = Xilinx XADC
(W)
bit 7 = 1 to enter select mode, 0 to enter selected device mode (no other bits have effect)
bit 6 = 1 to change selected device
bits 1:0 selected device
00 = none
01 = Xilinx DNA
10 = Xilinx XADC
* Xilinx DNA Mode
(R)
bit 0 = dna bit (serial stream shifts left)
the first eight bits read will indicate the length of the following dna bits
(W)
bit 7 = 1 to enter select mode (write has no other effect)
otherwise causes dna string to reload, ready for fresh read
* Xilinx XADC Mode (Documented in Xilinx Series 7 UG480)
(R)
bit 6 = 1 if XADC is busy with conversion (BUSY)
bit 1 = 1 if XADC conversion completed since last read (EOC, read clears)
bit 0 = 1 if XADC conversion sequence completed since last read (EOS, read clears)
(W)
bit 7 = 1 to enter select mode (write has no other effect)
bit 6 = 1 to reset XADC (RESET)
bit 0 = 1 to start conversion (CONVST)
* Re-enter select mode at any time by writing to the register with bit 7 set
* Select a device to communicate with by writing to the register with bits 6 & 7 set
* Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg

I/O Trap Cause Register

2024-11-03T12:47:44Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$DA
|Readable=Yes
|Writable=No
|ShortDesc=experimental
}}
0 = none (zero at the same time nextreg 0x02 bit 4 is 0)
1 = port_2ffd read
2 = port_3ffd read
3 = port_3ffd write
* If nextreg 0x02 bit 4 indicates an i/o cycle was trapped, this register indicates the cause

I/O Trap Write Register

2024-11-03T12:41:37Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$D9
|Readable=Yes
|Writable=Yes
|ShortDesc=experimental
}}
Holds byte written during trapped i/o write cycle

I/O Traps Register

2024-11-03T12:40:47Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$D8
|Readable=Yes
|Writable=Yes
|ShortDesc=experimental
}}
bits 7:1 = Reserved must be zero
bit 0 = 1 to enable +3 FDC traps on ports 0x2ffd and 0x3ffd
* An i/o trap generates a multiface nmi and is indicated in nextreg 0x02
* Traps cannot be triggered by the dma or while the multiface, divmmc or external nmi is active

DMA interrupt enable 2

2024-11-03T12:37:16Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$CE
|Readable=Yes
|Writable=Yes
|ShortDesc=UART Interrupts that can override DMA
}}
bit 7 = Reserved must be zero
bit 6 = UART1 Tx empty
bit 5 = UART1 Rx half full \ shared
bit 4 = UART1 Rx available / interrupt
bit 3 = Reserved must be zero
bit 2 = UART0 Tx empty
bit 1 = UART0 Rx half full \ shared
bit 0 = UART0 Rx available / interrupt
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode

soft reset = 0x00

Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.

DMA interrupt enable 1

2024-11-03T12:35:19Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$CD
|Readable=Yes
|Writable=Yes
|ShortDesc=CTC Interrupts that can override DMA
}}
bit 7 = ctc channel 7 zc/to
bit 6 = ctc channel 6 zc/to
bit 5 = ctc channel 5 zc/to
bit 4 = ctc channel 4 zc/to
bit 3 = ctc channel 3 zc/to
bit 2 = ctc channel 2 zc/to
bit 1 = ctc channel 1 zc/to
bit 0 = ctc channel 0 zc/to
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode

soft reset = 0x00

Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.

DMA interrupt enable 0

2024-11-03T12:34:56Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$CC
|Readable=Yes
|Writable=Yes
|ShortDesc=Interrupts that can override DMA
}}
bit 7 = NMI
bit 1 = Line
bit 0 = ULA
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode

Soft reset = 0x00

Because interrupts are only sampled at the end of an instruction by the Z80, each time the dma is interrupted one instruction of progress is made in the main program.

DMA interrupt enable 2

2024-11-03T12:33:29Z

Sol HSA: updated to 78a6ee50

DMA interrupt enable 1

2024-11-03T12:32:21Z

Sol HSA: updated to 78a6ee50

DMA interrupt enable 0

2024-11-03T12:31:10Z

Sol HSA: updated to 78a6ee50

Interrupt Status 2 Register

2024-11-03T12:29:37Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$CA
|Readable=Yes
|Writable=Yes
|ShortDesc=Has UART interrupt happened?
}}
bit 7 = Reserved must be zero
bit 6 = UART1 Tx empty
bit 5 = UART1 Rx half full \ shared
bit 4 = UART1 Rx available / interrupt
bit 3 = Reserved must be zero
bit 2 = UART0 Tx empty
bit 1 = UART0 Rx half full \ shared
bit 0 = UART0 Rx available / interrupt
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared

Interrupt Status 1 Register

2024-11-03T12:28:32Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C9
|Readable=Yes
|Writable=Yes
|ShortDesc=has ctc interrupt occurred?
}}
bit 7 = ctc channel 7 zc/to
bit 6 = ctc channel 6 zc/to
bit 5 = ctc channel 5 zc/to
bit 4 = ctc channel 4 zc/to
bit 3 = ctc channel 3 zc/to
bit 2 = ctc channel 2 zc/to
bit 1 = ctc channel 1 zc/to
bit 0 = ctc channel 0 zc/to
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared

Interrupt Status 0 Register

2024-11-03T12:27:07Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C8
|Readable=Yes
|Writable=Yes
|ShortDesc=has interrupt occurred?
}}
bits 7:2 = Reserved must be 0
bit 1 = Line
bit 0 = ULA
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the interrupt pending condition is cleared

Interrupt Enable 2 Register

2024-11-03T12:25:13Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C6
|Readable=Yes
|Writable=Yes
|ShortDesc=UART interrupt enable control
}}
bit 7 = Reserved must be zero
bit 6 = UART1 Tx empty
bit 5 = UART1 Rx near full \ shared
bit 4 = UART1 Rx available / interrupt
bit 3 = Reserved must be zero
bit 2 = UART0 Tx empty
bit 1 = UART0 Rx near full \ shared
bit 0 = UART0 Rx available / interrupt
* Rx near full overrides Rx available
* If a device interrupt is disabled, it enters a polled mode

Soft reset = 0x00

Interrupt Enable 1 Register

2024-11-03T12:23:47Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C5
|Readable=Yes
|Writable=Yes
|ShortDesc=ctc interrupt enable control
}}
bit 7 = ctc channel 7 zc/to
bit 6 = ctc channel 6 zc/to
bit 5 = ctc channel 5 zc/to
bit 4 = ctc channel 4 zc/to
bit 3 = ctc channel 3 zc/to
bit 2 = ctc channel 2 zc/to
bit 1 = ctc channel 1 zc/to
bit 0 = ctc channel 0 zc/to
* If a device interrupt is disabled, it enters a polled mode

soft reset = 0x00

Interrupt Enable 0 Register

2024-11-03T12:22:23Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C4
|Readable=Yes
|Writable=Yes
|ShortDesc=Interrupt type enable control
}}
bit 7 = Expansion bus /INT (soft reset = 1)
bits 6:2 = Reserved must be 0
bit 1 = Line ** (soft reset = 0)
bit 0 = ULA ** (soft reset = 1)
* * If a device interrupt is disabled, it enters a polled mode
* ** Aliases of interrupt enable bits in nextreg 0x22

Soft reset = 0x81

NMI Return Address MSB Register

2024-11-03T12:20:14Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C3
|Readable=Yes
|Writable=Yes
|ShortDesc=MSB of NMI return address
}}
Soft reset = 0x00

The return address written during an nmi acknowledge cycle is always stored in these registers.

NMI Return Address LSB Register

2024-11-03T12:19:00Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C2
|Readable=Yes
|Writable=Yes
|ShortDesc=LSB of NMI return address
}}
Soft reset = 0x00

The return address written during an nmi acknowledge cycle is always stored in these registers.

Interrupt Control Register

2024-11-03T12:17:22Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$C0
|Readable=Yes
|Writable=Yes
}}
Soft reset = 0x00

bits 7:5 = Programmable portion of im2 vector*
bit 4 = Reserved must be 0
bit 3 = Enable stackless nmi response**
bits 2:1 = Current Z80 interrupt mode 0,1,2 (read only, write ignored)
bit 0 = Maskable interrupt mode: pulse (0) or hw im2 mode (1)

* * In hw im2 mode the interrupt vector generated is:
bits 7:5 = nextreg 0xC0 bits 7:5
bits 4:1 = 0 line interrupt (highest priority)
= 1 uart0 Rx
= 2 uart1 Rx
= 3-10 ctc channels 0-7
= 11 ula
= 12 uart0 Tx
= 13 uart1 Tx (lowest priority)
bit 0 = 0

* * In hw im2 mode the expansion bus is the lowest priority interrupter and if no vector is supplied externally then 0xFF is generated.

* ** The return address pushed during an nmi acknowledge cycle will be written to nextreg instead of memory (the stack pointer will be decremented) and the first RETN after the acknowledge will take its return address from nextreg instead of memory (the stack pointer will be incremented). If bit 3 = 0 and in other circumstances, RETN functions normally.

Divmmc Entry Points 1

2024-11-03T12:11:20Z

Sol HSA: Created page with "{{NextRegister |Number=$BB |Readable=Yes |Writable=Yes |ShortDesc=DivMMC automap control }} bit 7 = 1 to enable automap on addresses 0x3DXX (instruction fetch, instant, ROM3..."

{{NextRegister
|Number=$BB
|Readable=Yes
|Writable=Yes
|ShortDesc=DivMMC automap control
}}
bit 7 = 1 to enable automap on addresses 0x3DXX (instruction fetch, instant, ROM3) > TRDOS (soft reset = 1)
bit 6 = 1 to disable automap on addresses 0x1FF8-0x1FFF (instruction fetch, delayed) (soft reset = 1)
bit 5 = 1 to enable automap on address 0x056A (instruction fetch, delayed, ROM3) \ tape traps (soft reset = 0)
bit 4 = 1 to enable automap on address 0x04D7 (instruction fetch, delayed, ROM3) / nextzxos (better compatibility) (soft reset = 0)
bit 3 = 1 to enable automap on address 0x0562 (instruction fetch, delayed, ROM3) \ tape traps (soft reset = 1)
bit 2 = 1 to enable automap on address 0x04C6 (instruction fetch, delayed, ROM3) / esxdos + original divmmc (soft reset = 1)
bit 1 = 1 to enable automap on address 0x0066 (instruction fetch + button, instant) (soft reset = 0)
bit 0 = 1 to enable automap on address 0x0066 (instruction fetch + button, delayed) (soft reset = 1)

soft reset = 0xCD

Divmmc Entry Points Timing 0

2024-11-03T12:09:00Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$BA
|Readable=Yes
|Writable=Yes
|ShortDesc=Adjust delay of divmmc mapping
}}
bit 7 = 1 for instant mapping else delayed (0x0038)
bit 6 = 1 for instant mapping else delayed (0x0030)
bit 5 = 1 for instant mapping else delayed (0x0028)
bit 4 = 1 for instant mapping else delayed (0x0020)
bit 3 = 1 for instant mapping else delayed (0x0018)
bit 2 = 1 for instant mapping else delayed (0x0010)
bit 1 = 1 for instant mapping else delayed (0x0008)
bit 0 = 1 for instant mapping else delayed (0x0000)

soft reset = 0x00

Divmmc Entry Points Valid 0

2024-11-03T12:07:29Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$B9
|Readable=Yes
|Writable=Yes
|ShortDesc=DivMMC entry point validity
}}
bit 7 = 1 for always else only when rom3 is present (0x0038) (soft reset = 0)
bit 6 = 1 for always else only when rom3 is present (0x0030) (soft reset = 0)
bit 5 = 1 for always else only when rom3 is present (0x0028) (soft reset = 0)
bit 4 = 1 for always else only when rom3 is present (0x0020) (soft reset = 0)
bit 3 = 1 for always else only when rom3 is present (0x0018) (soft reset = 0)
bit 2 = 1 for always else only when rom3 is present (0x0010) (soft reset = 0)
bit 1 = 1 for always else only when rom3 is present (0x0008) (soft reset = 0)
bit 0 = 1 for always else only when rom3 is present (0x0000) (soft reset = 1)

soft reset = 0x01

Divmmc Entry Points 0

2024-11-03T12:05:18Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$B8
|Readable=Yes
|Writable=Yes
|ShortDesc=DivMMC automap control
}}
bit 7 = 1 to enable automap on address 0x0038 (instruction fetch) (soft reset = 1)
bit 6 = 1 to enable automap on address 0x0030 (instruction fetch) (soft reset = 0)
bit 5 = 1 to enable automap on address 0x0028 (instruction fetch) (soft reset = 0)
bit 4 = 1 to enable automap on address 0x0020 (instruction fetch) (soft reset = 0)
bit 3 = 1 to enable automap on address 0x0018 (instruction fetch) (soft reset = 0)
bit 2 = 1 to enable automap on address 0x0010 (instruction fetch) (soft reset = 0)
bit 1 = 1 to enable automap on address 0x0008 (instruction fetch) (soft reset = 1)
bit 0 = 1 to enable automap on address 0x0000 (instruction fetch) (soft reset = 1)

Soft reset = 0x83

Extended MD Pad Buttons Register

2024-11-03T12:01:06Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$B2
|Readable=Yes
|Writable=No
|ShortDesc=Reading additional buttons on MD pads
}}
bit 7 = 1 if Right Pad X pressed
bit 6 = 1 if Right Pad Z pressed
bit 5 = 1 if Right Pad Y pressed
bit 4 = 1 if Right Pad MODE pressed
bit 3 = 1 if Left Pad X pressed
bit 2 = 1 if Left Pad Z pressed
bit 1 = 1 if Left Pad Y pressed
bit 0 = 1 if Left Pad MODE pressed

Extended Keys 1 Register

2024-11-03T11:56:50Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$B1
|Readable=Yes
|Writable=No
|ShortDesc=Read Next keyboard compound keys separately
}}
Available since core3.1.5.

{|class="wikitable"
! Bit !! Description
|-
| 7 || 1 if DELETE pressed
|-
| 6 || 1 if EDIT pressed
|-
| 5 || 1 if BREAK pressed
|-
| 4 || 1 if INV VIDEO pressed
|-
| 3 || 1 if TRUE VIDEO pressed
|-
| 2 || 1 if GRAPH pressed
|-
| 1 || 1 if CAPS LOCK pressed
|-
| 0 || 1 if EXTEND pressed
|}

* Nextreg 0x68 bit 4 stops extended keys from making entries in the 8x5 matrix

{{NextRegNo|$68}} (104) bit 4 stops extended keys from making entries in the 8x5 matrix

Extended Keys 0 Register

2024-11-03T11:56:18Z

Sol HSA: updated to 78a6ee50

{{NextRegister
|Number=$B0
|Readable=Yes
|Writable=No
|ShortDesc=Read Next keyboard compound keys separately
}}
Available since core3.1.5.

{|class="wikitable"
! Bit !! Description
|-
| 7 || 1 if ; pressed
|-
| 6 || 1 if " pressed
|-
| 5 || 1 if , pressed
|-
| 4 || 1 if . pressed
|-
| 3 || 1 if UP pressed
|-
| 2 || 1 if DOWN pressed
|-
| 1 || 1 if LEFT pressed
|-
| 0 || 1 if RIGHT pressed
|}

* Nextreg 0x68 bit 4 stops extended keys from making entries in the 8x5 matrix

{{NextRegNo|$68}} (104) bit 4 stops extended keys from making entries in the 8x5 matrix