SpecNext Wiki - User contributions [en-gb]

Xilinx-Artix-7 FPGA

2025-07-19T09:27:31Z

Mikecad:

== FPGA Upgrade: Artix-7 vs Spartan-6 ==

The ZX Spectrum Next Kickstarter model KS2 (Issue 4 board) uses the '''Xilinx Artix-7 XC7A15T FPGA''', replacing the '''Xilinx Spartan-6 XC6SLX16 FPGA''' used in the original KS1 (Issue 2B board). The Artix-7 is a more modern device, offering better performance, lower power consumption, and access to newer development tools.

The KS3 will use an Artix-7 XC7A35T-2 which pretty much doubles the logic cells, block RAM and DSP slices.

Below is a comparison between the three FPGAs:

{| class="wikitable"
! Feature !! Spartan-6 XC6SLX16 (KS1 - Issue 2B) !! Artix-7 XC7A15T (KS2 - Issue 4) !! Artix-7 XC7A35T-2 (KS3)
|-
| Technology Node || 45 nm || 28 nm || 28nm
|-
| Logic Cells || ~14,579 || ~16,640 || ~33,280
|-
| Flip-Flops || 18,224 || 20,800 || 41,600
|-
| Block RAM || 576 Kbits || 918 Kbits || 1,800 Kbits
|-
| DSP Slices || 32 || 45 || 90
|-
| Power Consumption || Higher || Lower (static & dynamic) || Lower (static & dynamic)
|-
| Clock Management || PLL-based || MMCMs and PLLs (more flexible) || MMCMs and PLLs (more flexible)
|-
| Toolchain || Xilinx ISE (legacy) || Xilinx Vivado (modern) || Xilinx Vivado (modern)
|-
| Partial Reconfiguration || Not supported || Supported || Supported
|}

Although the Spartan and Artix FPGA models require different bitstreams due to the differing FPGA architectures, all systems are designed to remain '''feature-identical wherever possible''' in the Next Core to avoid splitting the user base. The KS2 and KS3 larger FPGA's could provide alternate cores with extra features - e.g. the Official QL core has Sprites on a KS2 to create an enhanced QL.

The only additions exclusive to KS2 (Issue 4) are four extra {{Category:Next_Configuration_Registers}} used for low-level hardware access:

* {{NextRegNo|$F0}} – XDEV CMD
* {{NextRegNo|$F8}} – XADC REG
* {{NextRegNo|$F9}} – XADC D0
* {{NextRegNo|$FA}} – XADC D1

These registers allow developers to interact with internal Xilinx features such as the DNA ID and XADC (analog-to-digital converter). Technical documentation for these registers can be found on their respective pages.

== External Links ==
* [https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf Xilinx Spartan-6 XC6SLX16 Data Sheet]
* [https://docs.amd.com/v/u/en-US/ds180_7Series_Overview Xilinx Artix-7 XC7A15T CSG324-1 Data Sheet]

Xilinx-Artix-7 FPGA

2025-07-19T09:24:55Z

Mikecad:

== FPGA Upgrade: Artix-7 vs Spartan-6 ==

The ZX Spectrum Next Kickstarter model KS2 (Issue 4 board) uses the '''Xilinx Artix-7 XC7A15T FPGA''', replacing the '''Xilinx Spartan-6 XC6SLX16 FPGA''' used in the original KS1 (Issue 2B board). The Artix-7 is a more modern device, offering better performance, lower power consumption, and access to newer development tools.

The KS3 will use an Artix-7 XC7A35T-2 which pretty much doubles the logic cells, block RAM and DSP slices.

Below is a comparison between the three FPGAs:

{| class="wikitable"
! Feature !! Spartan-6 XC6SLX16 (KS1 - Issue 2B) !! Artix-7 XC7A15T (KS2 - Issue 4) !! Artix-7 XC7A35T-2 (KS3)
|-
| Technology Node || 45 nm || 28 nm || 28nm
|-
| Logic Cells || ~14,579 || ~16,640 || ~33,280
|-
| Flip-Flops || 18,224 || 20,800 || 41,600
|-
| Block RAM || 576 Kbits || 918 Kbits || 1,800 Kbits
|-
| DSP Slices || 32 || 45 || 90
|-
| Power Consumption || Higher || Lower (static & dynamic) || Lower (static & dynamic)
|-
| Clock Management || PLL-based || MMCMs and PLLs (more flexible) || MMCMs and PLLs (more flexible)
|-
| Toolchain || Xilinx ISE (legacy) || Xilinx Vivado (modern) || Xilinx Vivado (modern)
|-
| Partial Reconfiguration || Not supported || Supported || Supported
|}

Although the two FPGA models require different bitstreams due to the differing FPGA architectures, all systems are designed to remain '''feature-identical wherever possible''' in the Next Core to avoid splitting the user base. The KS2 and KS3 larger FPGA's could provide alternate cores with extra features - e.g. the Official QL core has Sprites on a KS2 to create an enhanced QL.

The only additions exclusive to KS2 (Issue 4) are four extra {{Category:Next_Configuration_Registers}} used for low-level hardware access:

* {{NextRegNo|$F0}} – XDEV CMD
* {{NextRegNo|$F8}} – XADC REG
* {{NextRegNo|$F9}} – XADC D0
* {{NextRegNo|$FA}} – XADC D1

These registers allow developers to interact with internal Xilinx features such as the DNA ID and XADC (analog-to-digital converter). Technical documentation for these registers can be found on their respective pages.

== External Links ==
* [https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf Xilinx Spartan-6 XC6SLX16 Data Sheet]
* [https://docs.amd.com/v/u/en-US/ds180_7Series_Overview Xilinx Artix-7 XC7A15T CSG324-1 Data Sheet]

Circuit Diagrams

2023-12-10T11:04:11Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=25%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== J15 - Next GPIO - Issue 4 ==

{| width=100%
|valign=top width=40%| [[Image:J15-I4-GPIOLocation.png]]
|valign=top| [[Image:J15-I4-CircuitGPIO.png]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

Circuit Diagrams

2023-12-10T11:03:27Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=25%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== J15 - Next GPIO - Issue 4 ==

{| width=100%
|valign=top width=30%| [[Image:J15-I4-GPIOLocation.png]]
|valign=top| [[Image:J15-I4-CircuitGPIO.png]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

Circuit Diagrams

2023-12-10T11:01:08Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=25%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== J15 - Next GPIO - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J15-I4-GPIOLocation.png]]
|valign=top| [[Image:J15-I4-CircuitGPIO.png]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

Circuit Diagrams

2023-12-10T11:00:05Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=25%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== J15 - Next GPIO - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J15-I4-GPIOLocation.png]]
|valign=top width=70%| [[Image:J15-I4-CircuitGPIO.png]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

File:J15-I4-CircuitGPIO.png

2023-12-10T10:58:12Z

Mikecad:

File:J15-I4-GPIOLocation.png

2023-12-10T10:57:34Z

Mikecad:

Circuit Diagrams

2023-12-10T10:56:30Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=25%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== J15 - Next GPIO - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J15-I4-GPIOLocation.png]]
|valign=top width=50%| [[Image:J15-I4-CircuitGPIO.png]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

Circuit Diagrams

2023-12-10T10:45:07Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=25%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

Circuit Diagrams

2023-12-10T10:44:11Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top width=50%| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

File:J13-I4-CircuitDaughterBoard.png

2023-12-10T10:43:14Z

Mikecad:

File:J13-I4-DaughterLocation.png

2023-12-10T10:42:31Z

Mikecad:

Circuit Diagrams

2023-12-10T10:41:56Z

Mikecad:

== Schematics ==

The KS1 and KS2 schematics can be downloaded [https://gitlab.com/thesmog358/tbblue/-/tree/master/docs/schematics?inline=false here].

The three tail matrix keyboard schematic can be downloaded [https://github.com/Threetwosevensixseven/NXtel/wiki/images/NS58A-5-01-04.pdf here].

== J13 - Daughter board connector - Issue 2A/2B ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J13 - Daughter board connector - Issue 4 ==

{| width=100%
|valign=top width=50%| [[Image:J13-I4-DaughterLocation.png]]
|valign=top| [[Image:J13-I4-CircuitDaughterBoard.png]]
|}

 

== J15 - Next GPIO ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

Notes:
* In VGA mode (scandoubler enabled), H-SYNC and V-SYNC are carried separately on their respective pins.
* In RGB mode (scandoubler disabled), H-SYNC carries composite sync, and V-SYNC carries 1.
* Pin 14 carries 3V3, which can be connected to SCART pin 16 to indicate RGB to the display.
* There is no convenient source of voltages between 9.5-12V to indicate 4:3 aspect ratio to the display on SCART pin 8, so this is usually left unconnected.

 

== CN8 - Digital Port ==

{| width=100%
|valign=top width=50%|[[Image:Digital Port Location.jpg]]
|valign=top| [[Image:Next Digital Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

 

== CN9 - ESP8266-01/RS-232 Port ==
{| width=100%
|valign=top width=50%| [[Image:Wifi_Port_Location.jpg]]
|valign=top| [[Image:Next_ESP_Port.png]]
|}

Main Page

2019-04-26T16:20:58Z

Mikecad:

Video Modes

2019-04-20T12:50:48Z

Mikecad: Mikecad moved page Enhanced ULA to Video Modes without leaving a redirect

The ULA is the Spectrum video and input chip. The Enhanced ULA adds extra video modes and features to the standard Spectrum.

ULA stands for "Uncommitted Logic Array" and refers to the manufacturing process involved. It does not relate to the video behavior of the chip. The chip itself is a custom chip.

= Spectrum Video Mode =
The standard Spectrum has only one video mode, with a resolution of 256x192 (not including the border) and 15 colours. This screen is further divided into 8x8 "attribute cells", so the attribute cell resolution is 32x24.

The ULA reads memory from [[Memory map|16k-Bank 5]] or [[Memory map|16k-Bank 7]] based on the setting at {{PortNo|$7FFD}}. If you haven't done any fancy messing about with the memory map, or you're using Spectrum 48k mode, then the screen memory will start at $4000.

There is one bit per pixel, so each byte represents 8 pixels (ie, one line of an attribute cell). Each screen line is stored in straightforward left-to-right order, so the 32 bytes from $4000 onwards represent all the pixels on the first line of the screen. Each 1 bit means the pixel is drawn in the "ink" color; a 0 bit means it is drawn in the "paper" color. Which colors these are is specified in the attribute blocks described below.

Unfortunately, while the columns of the screen are in straightforward order, the ''lines'' are not. The 192 line screen is vertically divided into thirds, with each third containing 64 lines (or 8 attribute cells). These three thirds are stored sequentially in memory, but ''within'' each third, the order is not what you'd expect. You'd expect it'd store the first line of the first cell, the second line of the first cell.. up to the eighth line of the first cell, then the first line of the second cell. Instead, the sorting is ''inverted''. So it stores the first line of the first cell, then the ''first line of the second cell'', then the first line of the third cell, and so on.. up to the first line of the eighth cell, which is then followed by the second line of the first cell!

This means that getting the address of the start of a given line can be a tricky business. The Spectrum Next provides the [[Extended Z80 instruction set|PIXELAD]] opcode to automatically perform the necessary transition. It can be done manually by breaking the line number (0-191) into bits as described below.

[[File:Ktclash.png|200px|thumb|left|Color clash in a classic spectrum game. The corners of the knight's helmet appear green and red because they are in the same attribute cell as the plant and table respectively.]]
Pixel data is stored with 1-bit color in the pixel data memory. However, it is possible for the color to vary across the screen. The snag is that you can set only two colours within a single ''attribute cell'' - that is, an 8x8 area. Because you can have only one color value per 8x8 cell, some older games exhibited "color clash" in which an object or part of an object would appear the wrong color because it needed to be drawn inside an 8x8 cell with another object of a different color.

Color data is stored at $5800 onwards. Unlike the pixel data, it's stored in straightforward reading order, with one byte per attribute cell, for a total of 768 bytes. The byte represents:

{|class="wikitable"
! Bit !! Function
|-
| 0-2 || "Ink" color (color of 1 bits). From 0-7: black, blue, red, magenta, green, cyan, yellow, white.
|-
| 3-5 || "Paper" color (color of 0 bits).
|-
| 6 || Bright flag (toggles brighter version of both colors).
|-
| 7 || Flash flag (toggles regular alternation of ink and paper colors)
|}

If Enhanced ULA is enabled, then this no longer applies; see below.

== Calculating line addresses in interleaved video modes ==

The line number can be broken down into bits as follows:

{| class=wikitable
! 128 !! 64 !! 32 !! 16 !! 8 !! 4 !! 2 !! 1
|-
| 3rd || 3rd || V-Cell || V-Cell || V-Cell || Offset || Offset || Offset
|}

Each 3rd is 64 lines, so the top two bits of the line number indicate which 3rd we're in, with the highest being %10 for 128 (%11 would be 192, off the bottom of the screen). Then, each cell is 8 lines, so bits 3-5 of the line number give the cell address, and the remaining bits give the line within that cell.

The thirds are stored in sequential order; each third contains 64 lines; and storing a line takes 32 bytes. This means each 3rd takes 2048 bytes, so the "which 3rd" number is multiplied by 2048. Add $4000 for the start of the screen and that'll give the address of the start of the target third. Now we need to get to the block for the correct line number. To store the top line of a single row of cells takes 32 bytes; but since all the top lines for 8 cells are stored together, there's actually 256 bytes (32*8) between lines. So the line number must be multiplied by 256 and added to the address. Then, to select the correct cell within that block, the cell number needs to be multiplied by 32 (because each line takes 32 bytes). So the final 16-bit address is:

{| class=wikitable
! 32768 !! 16384 !! 8192 !! 4096 !! 2048 !! 1024 !! 512 !! 256 !! 128 !! 64 !! 32 !! 16 !! 8 !! 4 !! 2 !! 1
|-
| 0 || 1 || 0 || 3rd || 3rd || Offset || Offset || Offset || V-Cell || V-Cell || V-Cell || 0 || 0 || 0 || 0 || 0
|}

The five lowest bits of this value are then used to select between the 32 horizontal cells on that line, which is simply done by dividing the pixel address by 8.

= Enhanced video modes =
The Next adds a number of additional video modes to the standard ULA.

== Timex Sinclair Double Buffering ==
Writing %001 to the lower 3 bits of {{PortNo|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (see [[Memory map]]) which can be combined with this - although the 128K modes CANNOT be used with Layer2 due to sharing BRAM in the FPGA.

== Timex Sinclair Hi-Res Mode ==
Writing %110 to the lower 3 bits of {{PortNo|$xxFF}} will change the screen resolution to 512x192, doubling the X resolution. This still uses the Double Buffer structure of one set of screen data at $4000 and another at $6000, but now columns (one column = one byte = 8 pixels) are alternately read from the two buffers to account for the higher resolution. In addition, attributes are disabled: this mode supports only two colors. Which they are can be set by writing bits 3-5 of {{PortNo|$xxFF}}.

== Timex Sinclair Hi-Color Mode ==
Writing %010 to the lower 3 bits of {{PortNo|$xxFF}} will disable the standard attribute area. Instead, the attribute area is set to begin at $6000 and to have the same interleaved structure as the pixel data. Each attribute byte is now applied to only one ''line'' of each cell, rather than the whole cell. The storage structure matches that of the pixel data (including the weird interleaving). This means that the areas of color clash are now limited to 8x1 blocks instead of 8x8 blocks.

== LoRes Layer/Radasjimian Mode ==
LoRes Layer is a mode similar to the "Radastanian Mode" on the ZXUno, in that it offers reduced resolution in exchange for more colors. LoRes Layer allows any of 256 colors anywhere on the screen, but lowers the resolution in both dimensions to 128x96.

LoRes layer is enabled by setting bit 7 in {{NextRegNo|$15}}. Each pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $5800, and the second 48 between $6000 and $7800. Each byte is an index into the ULA palette.

== Enhanced ULA ==

The Spectrum Next comes with Enhanced ULA which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].

Setting bit 0 of {{NextRegNo|$43}} enables the Enhanced ULA mode. In this mode the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.

= Additional features =
In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.

Main Page

2019-04-20T12:49:06Z

Mikecad: /* Video */

== References ==

=== System architecture ===
* [[Extended Z80 instruction set]]
* [[Memory map]] and switching mechanics
* [[Reference machines]] and timing
* [[Boot Sequence]]
* [[Board feature control]] and port list
* [[Interrupts]]
* [[RPi0 Acceleration]]
* [[DMA]]
* [[Copper]]
* [[file formats]]
* [[Z80 programming]]

=== Video ===
* [[Video Modes]]
* [[Tilemap]]
* [[Sprites]]
* [[Layer 2]]
* [[Palettes]]

=== Audio ===
* [[Turbo Sound Next]]
* [[SpecDrum/DAC]]

=== Firmware ===
* [[NextZXOS]]
* [[ESXDOS]]
* [[NextBASIC]]
* [[System Variables]]

=== Electronics ===
* [[Circuit Diagrams]]

== Development Tools ==

=== Emulators ===

See main page: [[Emulators]]

=== Assemblers ===
Any Z80 assembler can produce code suitable for the Next. However, the Next and most emulators cannot load raw blocks of Z80 code, so a Spectrum specific tool will be useful for creating .TZX or .TAP files with the necessary loaders.

* ''[http://www.desdes.com/products/oldfiles/zeus.htm Zeus-ish]''
: Provides a complete Z80 IDE and Macro assembler, scripted disassember plus an integrated Z80 emulator for a range of machines including partial Next support
: Supports the Next opcodes directly
: Supports remote debugging on the Next using ParaSys across a serial link
* ''[http://pasmo.speccy.org/ Pasmo]''
: A long established Z80 assembler, but has been out of development for a long time
: Supports all currently known Next extension opcodes through this [https://www.facebook.com/groups/specnext/512169722473686/ modified Pasmo from Russ McNulty and Tony Thompson] and also now supports outputting .sna files to use with CSpect, thanks to Russ McNulty
* ''SNasm'' - included with the [http://dailly.blogspot.co.uk/2017/08/cspect-v05.html CSpect] emulator
: Supports the Next extension opcodes directly
* ''z80asm'' - part of [https://github.com/z88dk/z88dk Z88dk]''
: Supports the Next extension opcodes directly, linking assembler with large z80 library, targets any memory configuration
* ''sjasmplus'' - [https://github.com/z00m128/sjasmplus z00m's fork]
: Supports all (core2.00.28) Next extension opcodes directly and it is under active development.

=== Compilers ===
* ''sccz80'' and ''zsdcc'' - part of [https://github.com/z88dk/z88dk Z88dk]
: "sccz80" is a small c derived c compiler that is nearly c90 compliant with a few notable exceptions. Emphasis is on small code.
: "zsdcc" is a fork of sdcc-z80 that is an open source optimizing c compiler with c90 and elements of c99 and c11 compliance.
: A Next target is present and under development. Output file types include tap, sna, and esxdos dot commands.
* ''[http://www.boriel.com/forum/zx-basic-compiler/ ZX Basic]''
: A Basic to Z80 compiler with extensions added to Sinclair Basic.

=== Hardware Expansion ===

Your next computer can be expanded internally to add additional functionality.
* RTC - Real Time Clock
* Accelerator - Raspberry Pi Zero
* ESP2866

* [[Expansion]] - working on page

* ''[https://www.specnext.com/forum/viewtopic.php?f=6&t=544 Specnext Forums]
: A link to the forums discussing hardware additions

= Community =

* [https://www.specnext.com/forum/ Official forums]
* [https://www.facebook.com/groups/specnext Facebook group]
* [https://specnext.slack.com/ Slack chat] ([https://join.slack.com/t/specnext/shared_invite/enQtMjQ2ODgzNTI5MzAzLWE2NzhhNjUzZGZhNWIxZWIyMTY4N2JmNTY3MWM4ZTkxOWY2M2UwZDQzN2FhYTEzNjFiY2I5MDA1MTc3NjVmYTI sign up])

= Sources =
* [[Bibliography]]

= Wiki "to do" list =
* [[Wiki TODO list]] (can be used also as warning which pages may contain outdated information)

Palette Value (9 bit colour) Register

2019-04-20T12:46:04Z

Mikecad: Mikecad moved page ULANext Palette Extension to Enhanced ULA Palette Extension without leaving a redirect: ULANext deprecated

{{NextRegister
|Number=$44
|Readable=Yes
|Writable=Yes
|ShortDesc=Use to set 9-bit (2-byte) colours of the ULANext palette, or to read second byte of colour.
}}
Two consecutive writes are needed to write the 9 bit colour:
* 1st write: bits 7-0 = RRRGGGBB
* 2nd write: bits 7-1 are reserved, must be 0 (except bit 7 for Layer 2), bit 0 = lsb B

(to detect whether first or second write is expected, one can read bit 7 of {{NextRegNo|$03}}, in case your code is not aware of current state)

If writing the Layer 2 palette colour, in the second byte, bit 7 is "priority" bit. Priority colour will be always on top (drawn above all other layers), even on a priority arrangement like "USL" . If you need the exact same colour with priority and non priority, you will need to program the same colour twice, changing bit 7 to 0 for the non priority colour alternative.

After the write of second byte, the palette index is auto-incremented, if the auto-increment is enabled by {{NextRegNo|$43}}.

The read will always read the second byte of colour (%p000000B) and it will not modify the index.

The modified palette remains until a Hard Reset.

ULANext Attribute Byte Format Register

2019-04-20T12:41:03Z

Mikecad: Mikecad moved page ULANext Ink Color Mask to Enhanced ULA Ink Color Mask without leaving a redirect: ULANext deprecated

{{NextRegister
|Number=$42
|Readable=Yes
|Writable=Yes
|ShortDesc=Specifies mask to extract ink colour from attribute cell value in ULANext mode.
}}
Bits 7-0 = Number of the last ink colour entry in palette (15 after a Reset).

This number can be 1, 3, 7, 15, 31, 63, 127 or 255. The HW behaviour for other values is unpredictable.

This value is used only when ULANext mode is enabled.

The 255 value enables the full ink colour mode and all the palette entries are inks. The paper and border colour is then taken from {{NextRegNo|$4A}}.

If the ink mask is not 255, then the zeroed part of mask signals which bits will be used to extract index of paper colour. Then this index is added to 128 and read from current palette (border index is also 128 + 0..7 value from port $FE). There are no "flash" or "bright" bits when ULANext mode is enabled, all eight attribute bits contribute either to ink or paper colour index.

Applies only to Enhanced ULA palette. Layer 2, Sprite and Tilemap palettes work as "full ink" or specifically to 4-bit graphics data.

ULA Palette Control Register

2019-04-20T12:30:09Z

Mikecad: Mikecad moved page ULANext Control Register to Enhanced ULA Control Register without leaving a redirect: ULANext is deprecated

{{NextRegister
|Number=$43
|Readable=Yes
|Writable=Yes
|ShortDesc=Enables or disables Enhanced ULA interpretation of attribute values and toggles active palette.
}}
{| class="wikitable"
! Bit !! Function
|-
| 7 || 1 to disable palette index write auto-increment
|-
| 6-4 || Select palette for reading or writing
|-
| 3 || Select Sprites palette (0 = first palette, 1 = second palette)
|-
| 2 || Select Layer 2 palette (0 = first palette, 1 = second palette)
|-
| 1 || Select ULA palette (0 = first palette, 1 = second palette)
|-
| 0 || Enabe ULANext mode if 1. (0 after a reset)
|}

Possible bits 6-4 for palette select (bit 6 selects first/second, 5-4 select type):
{| class="wikitable"
! Bits 6-4 !! selects
|-
| %000 || ULA first palette
|-
| %100 || ULA second palette
|-
| %001 || Layer 2 first palette
|-
| %101 || Layer 2 second palette
|-
| %010 || Sprites first palette
|-
| %110 || Sprites second palette
|-
| %011 || Tilemap first palette
|-
| %111 || Tilemap second palette
|}

ULA Palette Control Register

2019-04-20T12:12:34Z

Mikecad:

Video Modes

2019-04-20T12:07:45Z

Mikecad:

File:Ktclash.png

2019-04-20T12:00:58Z

Mikecad:

RPi0 Acceleration

2019-04-20T10:17:26Z

Mikecad:

The Spectrum Next has a 40 pin (20x2) male header to which a Raspberry Pi Zero (RPi0) can be connected. It is labelled [[Circuit_Diagrams#Accelerator_Board|Accelerator Board]] on the main board.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
Rpizerotop.jpg|RPi0 top
Rpizerobottom.jpg|RPi0 bottom
SpecNextBoardAcceleratorHeader.jpg|Male 40 pin header
SpecNextBoardAcceleratorFitted.jpg|RPi0 fitted
</gallery>

Circuit Diagrams

2019-04-20T10:15:47Z

Mikecad:

== J13 - Daughter board connector ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J15 - Next GPIO ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

 

== CN8 - HDMI Port ==

{| width=100%
|valign=top width=50%| [[Image:HDMI_Port_Location.jpg]]
|valign=top| [[Image:HDMI_Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Board ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

RPi0 Acceleration

2019-04-20T10:15:08Z

Mikecad:

The Spectrum Next has a 40 pin (20x2) male header to which a Raspberry Pi Zero (RPi0) can be connected. It is labelled [[Circuit_Diagrams#Accelerator_port|Accelerator Board]] on the main board.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
Rpizerotop.jpg|RPi0 top
Rpizerobottom.jpg|RPi0 bottom
SpecNextBoardAcceleratorHeader.jpg|Male 40 pin header
SpecNextBoardAcceleratorFitted.jpg|RPi0 fitted
</gallery>

File:SpecNextBoardAcceleratorFitted.jpg

2019-04-20T10:14:30Z

Mikecad:

RPi0 Acceleration

2019-04-20T10:10:21Z

Mikecad:

RPi0 Acceleration

2019-04-20T10:09:10Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero (RPi0) can be connected. It is labelled [[Circuit_Diagrams#Accelerator_port|Accelerator Board]] on the main board.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
Rpizerotop.jpg|RPi0 top
Rpizerobottom.jpg|RPi0 bottom
SpecNextBoardAcceleratorHeader.jpg|Male 40 pin header
</gallery>

RPi0 Acceleration

2019-04-20T10:08:43Z

Mikecad:

File:SpecNextBoardAcceleratorHeader.jpg

2019-04-20T10:07:43Z

Mikecad:

RPi0 Acceleration

2019-04-20T10:06:12Z

Mikecad:

RPi0 Acceleration

2019-04-20T10:03:59Z

Mikecad:

RPi0 Acceleration

2019-04-20T10:03:05Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero (RPi0) can be connected and is labelled [[Circuit_Diagrams#Accelerator_port|Accelerator Board]] on the main board.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
Rpizerotop.jpg|RPi0 top
Rpizerobottom.jpg|RPi0 bottom
</gallery>

RPi0 Acceleration

2019-04-20T10:00:34Z

Mikecad:

RPi0 Acceleration

2019-04-20T09:59:24Z

Mikecad:

File:Rpizerobottom.jpg

2019-04-20T09:58:45Z

Mikecad:

RPi0 Acceleration

2019-04-20T09:56:15Z

Mikecad:

File:Rpizerotop.jpg

2019-04-20T09:55:00Z

Mikecad:

RPi0 Acceleration

2019-04-20T09:48:03Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero (RPi0) can be connected and is labelled [[Circuit_Diagrams#Accelerator_port|Accelerator Board]] on the main board.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
RpiZeroTop.jpg|Raspberry Pi Zero top
RpiZeroBottom.jpg|Raspberry Pi Zero bottom
</gallery>

RPi0 Acceleration

2019-04-20T09:45:55Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero (RPi0) can be connected and is labelled "[[https://specnext.dev/wiki/Circuit_Diagrams#Accelerator_Port|Accelerator Board]]" on the main board.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
RpiZeroTop.jpg|Raspberry Pi Zero top
RpiZeroBottom.jpg|Raspberry Pi Zero bottom
</gallery>

RPi0 Acceleration

2019-04-20T09:43:55Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero (RPi0) can be connected.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
RpiZeroTop.jpg|Raspberry Pi Zero top
RpiZeroBottom.jpg|Raspberry Pi Zero bottom
</gallery>

RPi0 Acceleration

2019-04-20T09:43:10Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero (RPi0) can be connected.

The RPi0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language, which may be more likely for this implementation.

It is not yet known how the RPi0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
RpiZeroTop.jpg|Raspberry Pi Zero top
RpiZeroBottom.jpg|Raspberry Pi Zero bottom
</gallery>

RPi0 Acceleration

2019-04-20T09:41:31Z

Mikecad:

The Spectrum Next has a 40 pin male header to which a Raspberry Pi Zero can be connected.

The Raspberry Pi 0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language, which may be more likely for this implementation.

It is not yet known how the Raspberry Pi Zero will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery>
RpiZeroTop.jpg|Raspberry Pi Zero top
RpiZeroBottom.jpg|Raspberry Pi Zero bottom
</gallery>

RPi0 Acceleration

2019-04-20T09:35:59Z

Mikecad:

The Spectrum Next has a 40 pin male header to which can be attached a Raspberry Pi Zero.

The Raspberry Pi 0 has a Broadcom BCM2835 SoC with an ARMv6 core, a Videocore 4 GPU, and its own 512 MB memory and HDMI output. It has its own SD card from which it boots. While it can traditionally run Linux, it can also be programmed "bare metal" directly in assembly language, which may be more likely for this implementation.

It is not yet known how the Raspberry Pi 0 will interface with the Spectrum Next. It was originally used to provide HDMI digital video and audio output for the Spectrum Next, but the HDMI functionality was moved onto the main board, making this original function redundant.

It is known that the Raspberry Pi versions supporting Wi-fi will not provide that Wi-fi to the Next.

== Attaching a Raspberry Pi Zero ==

To connect the RPi0 to the Spectrum Next, a 20x2 pin female header needs to be attached on the underside of the Pi:

<gallery widths=200px>
RPi0_2x20pinFemale.png|Header attached using solder
RPi0_2x20pinFemale_Hammer.png|Solder-less variety attached using a hammer
RPi0_1.jpg|Raspberry Pi Zero connected to the Spectrum Next
</gallery>

File:RTC Port Location.jpg

2019-04-16T06:13:59Z

Mikecad:

File:RTC Port.png

2019-04-16T06:11:03Z

Mikecad:

Circuit Diagrams

2019-04-16T06:10:42Z

Mikecad:

== J13 - Daughter board connector ==

{| width=100%
|valign=top width=50%| [[Image:DaughterLocation.jpg]]
|valign=top| [[Image:Circuit_daughter_board.png]]
|}

 

== J15 - Next GPIO ==

{| width=100%
|valign=top width=50%| [[Image:NEXT_GPIO_location.jpg]]
|valign=top width=50%| [[Image:NEXT_GPIO.png|461px]]
|}

 

== CN5 - Expansion bus (edge connector) ==

{| width=100%
|valign=top width=50%| [[Image:Expansion_bus_location.jpg]]
|valign=top| [[Image:Expansion_bus.png|461px]]
|}

 

== J10/J11 - Memory Expansion Ports ==

{| width=100%
|valign=top width=50%| [[Image:Mem_Expansion_location.jpg]]
|valign=top| [[Image:Mem_Expansion.png|461px]]
|}

 

== J4/J7 J8/J14 - Joystick Ports ==

{| width=100%
|valign=top width=50%| [[Image:Joystick_Ports_Location.jpg]]
|valign=top| [[Image:Joystick_Ports.png]]
|}

 

== CN1 - VGA Video Port ==

{| width=100%
|valign=top width=50%| [[Image:Video_Port_Location.jpg]]
|valign=top| [[Image:Video_Port.png]]
|}

 

== CN8 - HDMI Port ==

{| width=100%
|valign=top width=50%| [[Image:HDMI_Port_Location.jpg]]
|valign=top| [[Image:HDMI_Port.png]]
|}

 

== CN2/CN6/CN7 - SD Reader (Mainboard) (CN6 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader_Main.png]]
|}

 

== CN10/CN11/CN12 - SD Reader (Daughterboard) (CN12 on reverse) ==

{| width=100%
|valign=top width=50%| [[Image:SD_Reader_Daughter_Port_Location.jpg]]
|valign=top| [[Image:SD_Reader.png]]
|}

 

== Accelerator Port ==

{| width=100%
|valign=top width=50%| [[Image:Accelerator_Port_Location.jpg]]
|valign=top| [[Image:Accelerator_Port.png]]
|}

 

== Real Time Clock (RTC) ==

{| width=100%
|valign=top width=50%| [[Image:RTC_Port_Location.jpg]]
|valign=top| [[Image:RTC_Port.png]]
|}

File:Accelerator Port.png

2019-04-16T06:06:16Z

Mikecad:

File:Accelerator Port Location.jpg

2019-04-16T06:05:34Z

Mikecad: