Z80 Instruction Table NoSemantic

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Revision as of 14:58, 20 January 2025 by Johnnyo (talk | contribs) (link to z80 next specific table too)
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The following page is created by a script which transformed the semantic-generated output from the Z80_Instruction_Table as of 200250120 to this plain wikimedia page. It also contains all the instructions and doesn't break the table after EX DE, HL like the source page. To view only ZX Next specific instructions see the following plain table which is generated in the same way like this plain table: Z80Next_Only_Instruction_Table

Z80N Instruction Table
Mnemonic Status Addressing Mode 1 Addressing Mode 2 Flags: C N PV H Z S T-States Summary
ADC A, (HL) S Accumulator Indirect S 0 V S S S 7 A+=HL*+(CF?1:0)
ADC A, (IXY+d) S Accumulator Indexed S 0 V S S S 19 A+=(IXY+d)*+(CF?1:0)
ADC A, n S Accumulator Immediate S 0 V S S S 7 A+=n+(CF?1:0)
ADC A, r S Accumulator Register S 0 V S S S 4 A+=r+(CF?1:0)
ADC HL, BC/DE/HL/SP S Register Register S 0 V ! S S 15 HL+=rr+(CF?1:0)
ADD A, (HL) S Accumulator Indirect S 0 V S S S 7 A+=HL*
ADD A, (IXY+d) S Accumulator Indexed S 0 V S S S 19 A+=(IXY+d)*
ADD A, n S Accumulator Immediate S 0 V S S S 7 A+=n
ADD A, r S Accumulator Register S 0 V S S S 4 A+=r
ADD HL, BC/DE/HL/SP S Register Register S 0 - ! - - 11 HL+=rr
ADD HL/DE/BC, A E Register Register ? - - - - - 8 rr+=unsigned A
ADD HL/DE/BC, nn E Register Immediate - - - - - - 16 rr+=nn
ADD IXY, BC/DE/IXY/SP S Register Register S 0 - ! - - 15 IXY+=rr
AND (HL) S Indirect - 0 0 P 1 S S 7 A := A & HL*
AND (IXY+d) S Indexed - 0 0 P 1 S S 19 A := A & (IXY+d)*
AND n S Immediate - 0 0 P 1 S S 7 A := A & n
AND r S Register - 0 0 P 1 S S 4 A := A & r
BIT b,(HL) S Immediate Indirect - 0 ? 1 ! ? 12 HL*[b]==1?
BIT b,(IXY+d) S Immediate Indexed - 0 ? 1 ! ? 20 (IXY+d)*[b]==1?
BIT b,r S Immediate Register - 0 ? 1 ! ? 8 r[b]==1?
BRLC DE,B E - - - - - - - - 8 DE:=DE<<(B&15) OR DE>>(16-B&15)
BSLA DE,B E - - - - - - - - 8 DE:=DE<<(B&31)
BSRA DE,B E - - - - - - - - 8 DE:=signed(DE)>>(B&31)
BSRF DE,B E - - - - - - - - 8 DE:=~(unsigned(~DE)>>(B&31))
BSRL DE,B E - - - - - - - - 8 DE:=unsigned(DE)>>(B&31)
CALL Z/NZ/C/NC/PO/PE/P/M, nn S Address - - - - - - - 17 ; 10 if not cc if cc {SP-=2; SP*:=PC; PC:=nn}
CALL nn S Address - - - - - - - 17 SP-=2; SP*:=PC; PC:=nn
CCF S - - ! 0 - ! - - 4 CF:=!CF
CP (HL) S Indirect - S 1 V S S S 7 A-=HL*?
CP (IXY+d) S Indexed - S 1 V S S S 19 A-=(IXY+d)?
CP n S Immediate - S 1 V S S S 7 A-=n?
CP r S Register - S 1 V S S S 4 A-=r?
CPD S - - - 1 L S ! S 16 HL*==A?; HL--; BC--
CPDR S - - - 1 L S ! S 21x+16 do CPD while (!Z && BC>0)
CPI S - - - 1 L S ! S 16 HL*==A?; HL++; BC--
CPIR S - - - 1 L S ! S 21x+16 do CPI while (!Z && BC>0)
CPL S - - - 1 - 1 - - 4 A:=~A
DAA S - - ! - P ! S S 8 if(A&$0F>$09 or HF) A±=$06; if(A&$F0>$90 or CF) A±=$60 (± depends on NF)
DEC (HL) S Indirect - - 1 ! S S S 11 HL*--
DEC (IXY+d) S Indexed - - 1 ! S S S 23 (IXY+D)*--
DEC BC/DE/HL/SP S Register - - - - - - - 6 rr--
DEC IXY S Register - - - - - - - 10 rr--
DEC r S Register - - 1 ! S S S 4 r--
DI S - - - - - - - - 4 IFF1:=0; IFF2:=0
DJNZ n S Immediate - - - - - - - 13 B--; if B!=0 PC+=nn
EI S - - - - - - - - 4 IFF1:=1; IFF2:=1
EX (SP), HL S Indirect Register - - - - - - 19 swap(SP*,HL)
EX (SP), IXY S Indirect Register - - - - - - 23 swap(SP*,IXY)
EX AF, AF' S Register Register ! ! ! ! ! ! 4 swap(AF,AF')
EX DE, HL S Register Register - - - - - - 4 swap(DE,HL)
EXX S - - - - - - - - 4 swap(BC,BC');swap(DE,DE');swap(HL,HL')
HALT S - - - - - - - - 4 waits for interrupt
IM n S Immediate - - - - - - - 8 Interrupt mode:=n
IN (c) U Register - - 0 P 0 S S 12 in(BC)?
IN A, (n) S Accumulator Immediate - - - - - - 11 A := in(An)
IN r, (c) S Register Register - 0 P 0 S S 12 r := in(BC)
INC (HL) S Indirect - - 0 ! S S S 11 HL*++
INC (IXY+d) S Indexed - - 0 ! S S S 23 (IXY+d)*++
INC BC/DE/HL/SP S Register - - - - - - - 6 rr++
INC IXY S Register - - - - - - - 10 rr++
INC r S Register - - 0 ! S S S 4 r++
IND S - - ? 1 ? ? ! ? 16 HL*:=in(BC); HL--; B--
INDR S - - ? 1 ? ? 1 ? 21x+16 do IND while(B>0)
INI S - - ? 1 ? ? ! ? 16 HL*:=in(BC); HL++; B--
INIR S - - ? 1 ? ? 1 ? 21x+16 do INI while(B>0)
JP (C) E Register - ? ? ? ? ? ? 13 PC:=PC&$C000+IN(C)<<6
JP (HL) S Register - - - - - - - 4 PC:=HL (not PC:=HL*)
JP (IXY) S Register - - - - - - - 8 PC:=IXY (not PC:=IXY*)
JP Z/NZ/NC/C/PO/PE/P/M, nn S Address - - - - - - - 10 if cc PC:=nn
JP nn S Address - - - - - - - 10 PC:=nn
JR C/NC/Z/NZ, nn S Immediate - - - - - - - 12 ; 7 if not cc if cc PC+=nn
JR nn S Immediate - - - - - - - 12 PC+=nn
LD (BC/DE), A S Indirect Accumulator - - - - - - 7 rr* := A
LD (HL), n S Indirect Immediate - - - - - - 10 HL* := n
LD (HL),r S Indirect Register - - - - - - 7 HL* := r
LD (IXY+d), n S Indexed Immediate - - - - - - 19 (IXY+d)* := n
LD (IXY+d),r S Indexed Register - - - - - - 19 (IXY+D)* := r
LD (nn), A S Address Accumulator - - - - - - 13 (nn)* := A
LD (nn), BC/DE/SP/IXY S Address Register - - - - - - 20 (nn)* := rr
LD (nn), HL S Address Register - - - - - - 16 (nn)* := HL
LD A, (BC/DE) S Accumulator Indirect - - - - - - 7 A := rr*
LD A, (nn) S Accumulator Address - - - - - - 13 A := (nn)*
LD A, I S Accumulator Register - 0 ! 0 S S 9 A := I; P/V:=IFF2
LD A, R S Accumulator Register - 0 ! 0 S S 9 A := R; P/V:=IFF2
LD BC/DE/HL/SP, nn S Register Immediate - - - - - - 10 rr := nn
LD BC/DE/SP/IXY, (nn) S Register Address - - - - - - 20 rr := (nn)*
LD HL, (nn) S Register Address - - - - - - 16 HL := (nn)*
LD I, A S Register Accumulator - - - - - - 9 I := A
LD IXY, nn S Register Immediate - - - - - - 14 rr := nn
LD R, A S Register Accumulator - - - - - - 9 R := A
LD SP, HL S Register Register - - - - - - 6 SP := HL
LD SP, IXY S Register Register - - - - - - 10 SP := IXY
LD r, (HL) S Register Indirect - - - - - - 7 r := HL*
LD r, (IXY+d) S Register Indexed - - - - - - 19 r := (IXY+d)*
LD r, r' S Register Register - - - - - - 4 r := r'
LD r,n S Register Immediate - - - - - - 7 r := n
LDD S - - - 0 L 0 - - 16 DE*:=HL*; DE--; HL--; BC--
LDDR S - - - 0 0 0 - - 21x+16 do LDD while(BC>0)
LDDRX E - - - - - - - - 21/16 do LDDX while(BC>0)
LDDX E - - - - - - - - 16 {if HL*!=A DE*:=HL*;} DE++; HL--; BC--
LDI S - - - 0 L 0 - - 16 DE*:=HL*; DE++; HL++; BC--
LDIR S - - - 0 L 0 - - 21x+16 do LDI while(BC>0)
LDIRX E - - - - - - - - 21/16 do LDIX while(BC>0)
LDIX E - - - - - - - - 16 {if HL*!=A DE*:=HL*;} DE++; HL++; BC--
LDPIRX E - - - - - - - - 21/16 do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
LDWS E - - - 0 ! S S S 14 DE*:=HL*; INC L; INC D;
MIRROR A E Register - - - - - - - 8 A[76543210]:=A[01234567]
MUL d,e E - - - - - - - - 8 DE:=D*E
NEG S - - ! 1 ! S S S 8 A:=0-A
NEXTREG n, A E Immediate Accumulator - - - - - - 17 HwNextReg_n:=A
NEXTREG n,n' E Immediate Immediate - - - - - - 20 HwNextReg_n:=n'
NOP S - - - - - - - - 4 PC+=1
OR (HL) S Indirect - 0 0 P 0 S S 7 A := A OR HL*
OR (IXY+d) S Indexed - 0 0 P 0 S S 19 A := A OR (IXY+d)*
OR n S Immediate - 0 0 P 0 S S 7 A := A OR n
OR r S Register - 0 0 P 0 S S 4 A := A OR r
OTDR S - - ? 1 ? ? 1 ? 21x+16 do OUTD while (B>0)
OTIR S - - ? 1 ? ? 1 ? 21x+16 do OUTI while (B>0)
OUT (c),0 U Register Immediate - - - - - - 12 out(BC,0)
OUT (c),r S Register Register - - - - - - 12 out(BC,r)
OUT (n),A S Immediate Accumulator - - - - - - 11 out(An,A)
OUTD S - - ? 1 ? ? ! ? 16 B--; out(BC,HL*); HL--
OUTI S - - ? 1 ? ? ! ? 16 B--; out(BC,HL*); HL++
OUTINB E - - ? ? ? ? ? ? 16 out(BC,HL*); HL++
PIXELAD E - - - - - - - - 8 HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
PIXELDN E - - - - - - - - 8 if(HL&$0700!=$0700) HL+=256;else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20;else HL:=HL&$F81F+$0800
POP AF S Register - ! ! ! ! ! ! 10 rr:=SP*; SP+=2
POP BC/DE/HL S Register - - - - - - - 10 rr:=SP*; SP+=2
POP IXY S Register - - - - - - - 14 rr:=SP*; SP+=2
PUSH BC/DE/HL/AF S Register - - - - - - - 11 SP-=2; SP*:=rr
PUSH IXY S Register - - - - - - - 15 SP-=2; SP*:=rr
PUSH nn E Immediate - - - - - - - 23 SP-=2; SP*:=nn
RES b,(HL) S Immediate Register - - - - - - 15 HL*:=HL* & (~(1<<b))
RES b,(IXY+d) S Immediate Indexed - - - - - - 23 (IXY+d)*:=(IXY+d)* & (~(1<<b))
RES b,r S Immediate Register - - - - - - 8 r:=r & (~(1<<b))
RES r,b,(IX+d) U Immediate Indexed - - - - - - 23 (IX+d)*:=(IX+d)* & (~(1<<b)); r:=(IX+d)*
RET S - - - - - - - - 10 PC:=SP*; SP+=2
RET Z/NZ/C/NC/PO/PE/P/M S - - - - - - - - 11 ; 5 if not cc if cc {PC:=SP*; SP+=2}
RETI S - - - - - - - - 14 PC:=SP*; SP+=2
RETN S - - - - - - - - 14 IFF1:=IFF2; PC:=SP*; SP+=2
RL (HL) S Indirect - ! 0 P 0 S S 15 x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=CF; CF:=x
RL (IXY+d) S Indexed - ! 0 P 0 S S 23 x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=CF; CF:=x
RL r S Register - ! 0 P 0 S S 8 x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x
RL r,(IX+d) U Register Indexed ! 0 P 0 S S 23 x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=CF; CF:=x; r:=(IX+d)*
RLA S - - ! 0 - 0 - - 4 x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x
RLC (HL) S Indirect - ! 0 P 0 S S 15 x:=HL*[7]; HL*:=HL*<<1; HL*[0]:=x; CF:=x
RLC (IXY+d) S Indexed - ! 0 P 0 S S 23 x:=(IXY+d)*[7]; (IXY+d)*:=(IXY+d)*<<1; (IXY+d)*[0]:=x; CF:=x
RLC r S Register - ! 0 P 0 S S 8 x:=r[7]; r:=r<<1; r[0]:=x; CF:=x
RLC r,(IX+d) U Register Indexed ! 0 P 0 S S 23 x:=(IX+d)*[7]; (IX+d)*:=(IX+d)*<<1; (IX+d)*[0]:=x; CF:=x; r:=(IX+d)*
RLCA S - - ! 0 - 0 - - 4 x:=A[7]; A:=A<<1; A[0]:=x; CF:=x
RLD S - - - 0 P 0 S S 18 x=HL*; HL*[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]
RR (HL) S Indirect - ! 0 P 0 S S 15 x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=CF; CF:=x
RR (IXY+d) S Indexed - ! 0 P 0 S S 23 x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=CF; CF:=x
RR r S Register - ! 0 P 0 S S 8 x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x
RR r,(IX+d) U Register Indexed ! 0 P 0 S S 23 x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=CF; CF:=x; r=(IX+d)*
RRA S - - ! 0 - 0 - - 4 x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x
RRC (HL) S Indirect - ! 0 P 0 S S 15 x:=HL*[0]; HL*:=HL*>>1; HL*[7]:=x; CF:=x
RRC (IXY+d) S Indexed - ! 0 P 0 S S 23 x:=(IXY+d)*[0]; (IXY+d)*:=(IXY+d)*>>1; (IXY+d)*[7]:=x; CF:=x
RRC r S Register - ! 0 P 0 S S 8 x:=r[0]; r:=r>>1; r[7]:=x; CF:=x
RRC r,(IX+d) U Register Indexed ! 0 P 0 S S 23 x:=(IX+d)*[0]; (IX+d)*:=(IX+d)*>>1; (IX+d)*[7]:=x; CF:=x; r:=(IX+d)*
RRCA S - - ! 0 - 0 - - 4 x:=A[0]; A:=A>>1; A[7]:=x; CF:=x
RRD S - - - 0 P 0 S S 18 x=HL*; HL*[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]
RST n S Immediate - - - - - - - 11 CALL n
SBC A, (HL) S Accumulator Indirect S 1 V S S S 7 A-=(HL*+(CF?1:0))
SBC A, (IXY+d) S Accumulator Indexed S 1 V S S S 19 A-=((IXY+d)+(CF?1:0))
SBC A, n S Accumulator Immediate S 1 V S S S 7 A-=(n+(CF?1:0))
SBC A, r S Accumulator Register S 1 V S S S 4 A-=(r+(CF?1:0))
SBC HL, BC/DE/HL/SP S Register Register S 1 V ! S S 15 HL-=(rr+(CF?1:0))
SCF S - - 1 0 - 0 - - 4 CF:=1
SET b,(HL) S Immediate Register - - - - - - 15 HL*:=HL* OR (1<<b)
SET b,(IXY+d) S Immediate Indexed - - - - - - 23 (IXY+d)*:=(IXY+d)* OR (1<<b)
SET b,r S Immediate Register - - - - - - 8 r:=r OR (1<<b)
SET r,b,(IX+d) U Immediate Indexed - - - - - - 23 (IX+d)*:=(IX+d)* OR (1<<b); r:=(IX+d)*
SETAE E - - - - - - - - 8 A:=unsigned($80)>>(E&7)
SL1 (HL) U Indirect - ! 0 P 0 S S 15 HL*:=(HL*<<1)+1
SL1 (IXY+d) U Indexed - ! 0 P 0 S S 23 (IXY+d)*:=((IXY+d)*<<1)+1
SL1 r U Register - ! 0 P 0 S S 8 r:=(r<<1)+1
SL1 r,(IXY+d) U Register Indexed ! 0 P 0 S S 23 (IXY+d)*:=((IXY+d)*<<1)+1; r=(IXY+d)*
SLA (HL) S Indirect - ! 0 P 0 S S 15 HL*:=HL*<<1
SLA (IXY+d) S Indexed - ! 0 P 0 S S 23 (IXY+d)*:=(IXY+d)*<<1
SLA r S Register - ! 0 P 0 S S 8 r:=r<<1
SLA r,(IX+d) U Register Indexed ! 0 P 0 S S 23 (IX+d)*:=(IX+d)*<<1; r=(IX+d)*
SRA (HL) S Indirect - ! 0 P 0 S S 15 HL*:=HL*>>1 OR HL*[7]
SRA (IXY+d) S Indexed - ! 0 P 0 S S 23 (IXY+d)*:=(IXY+d)*>>1 OR (IXY+d)*[7]
SRA r S Register - ! 0 P 0 S S 8 r:=r>>1 OR r[7]
SRA r,(IX+d) U Register Indexed ! 0 P 0 S S 23 (IX+d)*:=(IX+d)*>>1 OR (IX+d)*[7]; r:=(IX+d)*
SRL (HL) S Indirect - ! 0 P 0 S 0 15 HL*:=unsigned(HL*)>>1
SRL (IXY+d) S Indexed - ! 0 P 0 S 0 23 (IXY+d)*:=unsigned((IXY+d)*)>>1
SRL r S Register - ! 0 P 0 S 0 8 r:=unsigned(r)>>1
SRL r,(IXY+d) U Register Indexed ! 0 P 0 S 0 23 (IXY+d)*:=unsigned((IXY+d)*)>>1; r:=(IXY+d)*
SUB (HL) S Indirect - S 1 V S S S 7 A -= HL*
SUB (IXY+d) S Indexed - S 1 V S S S 19 A -= (IXY+d)*
SUB n S Immediate - S 1 V S S S 7 A -= n
SUB r S Register - S 1 V S S S 4 A -= r
SWAPNIB E - - - - - - - - 8 A:=A[3210]<<4 OR A[7654]>>4
TEST n E Immediate - S ? P S S S 11 A&n?
XOR (HL) S Indirect - 0 0 P 0 S S 7 A := A ^ HL*
XOR (IXY+d) S Indexed - 0 0 P 0 S S 19 A := A ^ (IXY+d)*
XOR n S Immediate - 0 0 P 0 S S 7 A := A ^ n
XOR r S Register - 0 0 P 0 S S 4 A := A ^ r