UART Frame
From SpecNext official Wiki
| Number | $163B |
|---|---|
| Decimal | 5691 |
| Short desc. | UART Frame |
| Bit Mask | %0001 0110 0011 1011 |
| Readable | Yes |
| Writable | Yes |
| Subsystem | UART |
0x163B UART Frame (R/W) (hard reset = 0x18) bit 7 = 1 to immediately reset the Tx and Rx modules to idle and empty fifos bit 6 = 1 to assert break on Tx (Tx = 0) when Tx reaches idle bit 5 = 1 to enable hardware flow control * bits 4:3 = number of bits in a frame 11 = 8 bits 10 = 7 bits 01 = 6 bits 00 = 5 bits bit 2 = 1 to enable parity check bit 1 = 0 for even parity, 1 for odd parity bit 0 = 0 for one stop bit, 1 for two stop bits
- * The esp ignores hardware flow control
- * In joystick i/o mode only cts is available
Note: the bit 7 is "sticky", so to stop UART from continuing to reset an explicit reset of the bit 7 is needed. The "immediately" means that the emptying and clearing is completed in one cycle. Also consider that resetting the bit 7 too soon could result in UART continuing to perform transfers while the other side hasn't completed the transfer of a single byte, and data received after that point would still be invalid.