Layer 2
Layer 2 provides an additional screen layer at 256*192 256 colours, 320*240 256 colours or 640 * 512 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated screen / Tilemap. Information for selecting the resolution and banks can be found on NextReg $70 https://wiki.specnext.dev/Layer_2_Control_Register
Since core 3.0 the visible Layer 2 will not cause the slow down of CPU, even in 14MHz and 28MHz modes, the machine will operate at same speed as when Layer 2 is invisible.
This page is updated core2.0 info with core 3.0 changes, but may still lack some detail or contain some inaccuracy.
The Layer 2 screen occupies 48kiB, which is stored in 3 consecutive banks. By default, banks 8-10 are used for the visible Layer 2 screen and banks 11-13 for the shadow Layer 2 screen. These can be set using Layer 2 RAM Page Register ($12) and Layer 2 RAM Shadow Page Register ($13) (avoid banks 5 and 7 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).
Each pixel of Layer 2 is assigned 1 byte of video memory. This means Layer 2 consumes a total of 48kiB. Since the Spectrum banks are 16kiB, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16kiB.
Layer 2 is controlled via Layer 2 Access Port ($123B / 4667), which is bit mapped as follows:
| Bit | Description |
|---|---|
| 7-6 | Video RAM bank select (write/read paging) |
| 5-4 | Reserved, write 0 |
| 3 | Use Shadow Layer 2 for paging - Layer 2 RAM Shadow Page Register ($13) |
| 2 | Enable Layer 2 read-only paging |
| 1 | Layer 2 visible - Layer 2 RAM Page Register ($12)
Since core 3.0 this bit has mirror in Display Control 1 Register ($69) |
| 0 | Enable Layer 2 write-only paging |
When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by writes into slot 1, ie memory area $0000-$3fff (see Memory map). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you cannot READ the contents of Layer 2 via this mapping! Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 paging was disabled.
When bit 2 of $123B is set to 1 (new feature of core 3.0), the same area $0000-$3fff is remapped for read, allowing read access into Layer 2 bank selected by bits 3,6 and 7 (while write will still go into the regular ROM/RAM page).
With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).
Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and Tilemap graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8.
Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).
You can still use also the regular banking ports to switch in one of the Layer 2 banks in slot for at $C000 (or use the ZX Next MMU registers to map that RAM in other regions). This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.
Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.
Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.
System registers Layer 2 X Offset Register ($16) and Layer 2 Y Offset Register ($17) apply a pixel shift to all content in Layer 2, allowing scrolling effects to be created.
Since core 3.0 the visibility of Layer 2 is not affected by usage of ZX128 ULA-shadow (Bank 7) screen.
To use double-buffered scheme for Layer 2, think about Layer 2 RAM Page Register ($12) being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while Layer 2 RAM Shadow Page Register ($13) is related only to write-over-ROM paging functionality (Layer 2 Access Port ($123B / 4667)).