DivMMC Trap Enable 1 Register

Number	TBRegisterNumber::$B2
Readable	TBRegisterReadable::Yes
Writable	TBRegisterWritable::Yes
Short Description	[[ShortDesc::DivMMC trap configuration]]

core3.1.3 status: NOT IMPLEMENTED YET

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Possible implementation specs:

(hard reset = 0x83)

   bit 7 = (trap, delayed) enable 0x0038
   bit 6 = (trap, delayed) enable 0x0030
   bit 5 = (trap, delayed) enable 0x0028
   bit 4 = (trap, delayed) enable 0x0020
   bit 3 = (trap, delayed) enable 0x0018
   bit 2 = (trap, delayed) enable 0x0010
   bit 1 = (trap, delayed) enable 0x0008
   bit 0 = (trap, delayed) enable 0x0000