Memory Paging Control
| Number | $7FFD |
|---|---|
| Decimal | |
| Short desc. | Selects active RAM, ROM, and displayed screen. |
| Bit Mask | %01-- ---- ---- --0- |
| Readable | No |
| Writable | Yes |
| Subsystem | Memory map |
Selects the active memory page in slot 4 at $C000. See Memory map.
Any values written to this port should also be stored at $5B5C if any OS routines are in use.
| Bit | Effect |
|---|---|
| 6-7 | Undocumented |
| 5 | Lock memory paging (setting to 1 locks pages and cannot be unlocked until next reset (on regular ZX128)) |
| 4 | ROM select (0 = 128k editor, 1 = 48k basic) (low bit of ROM select on +2/+3) |
| 3 | Shadow Screen toggle (0 = bank 5, 1 = bank 7) - this is ULA layer shadow, not related to Layer 2 RAM Shadow Page Register ($13) |
| 0-2 | Bank number for slot 4 ($C000) |
Since core3.0 the Layer 2 can be used together with shadow ULA screen from Bank 7 (previous cores did disable Layer 2).
When the port is locked (bit 5), the shadow screen toggle is considered part of the paging, i.e. it's not possible to flip between shadow and regular screen. Except for Display Control 1 Register ($69) which works even when port is locked, and you can unlock the port back (without reset) with Peripheral 3 Register ($08).
ULA shadow screen from Bank 7 has higher priority than Timex modes, setting bit 3 to "1" when in one of the extended Timex graphic modes will switch to classic ZX128 ULA mode using Bank 7 data.