Video Line Interrupt Control Register
From SpecNext official Wiki
Revision as of 20:09, 22 December 2018 by wiki>Ped7g
| Number | $22 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Controls the timing of raster interrupts and the ULA frame interrupt. |
| Bit | Function |
|---|---|
| 7 | (R) INT signal (even when Z80N has interrupts disabled) (1 = interrupt is requested)
(W) Reserved, must be 0 |
| 6-3 | Reserved, must be 0 |
| 2 | If 1 disables original ULA interrupt (Reset to 0 after a reset) |
| 1 | If 1 enables Line Interrupt (Reset to 0 after a reset) |
| 0 | MSB of Line Interrupt line value (Reset to 0 after a reset) |