Generate Maskable Interrupt Register
From SpecNext Wiki
| Number | TBRegisterNumber::$20 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Trigger interrupt |
bit 7 = line bit 6 = ula bits 5:4 = reserved bits 3:0 = ctc 3:0
- Set bits on R indicate whether an interrupt occurred or is pending (alias of bits in NR 0xC8 - 0xCA)
- Set bits on W always generate a maskable interrupt ignoring enables (NR 0xC4 - 0xC6)