Memory map
The Next supports two memory management models which operate in tandem. One is a unique memory management system for the Next. The other is an expanded version of the memory manager from the original Spectrum 128 and +2/+3 series.
Contents
Global Memory Map
The total available RAM space of the Next is 768k on an unexpanded Next, or 1792k on a Next expanded to 2Mb. (The base Next has 1mb of memory but 256k of it is reserved for the ROMs and firmware.)
The Z80 processor in the Next can access only 64k of memory at a time, and so the memory is divided into banks which are used in determining which memory it sees. Spectrum 128k memory management, and NextBASIC, use 16k banks. Next memory management via machine code uses 8k banks.
| 16k-bank | 8k-bank | True Address | Size | Description |
|---|---|---|---|---|
| - | - | $000000-$00ffff | 64K | ZX Spectrum ROM |
| - | - | $010000-$013fff | 16K | EsxDOS ROM |
| - | - | $014000-$017fff | 16K | Multiface ROM |
| - | - | $018000-$01bfff | 16K | Multiface Extra ROM |
| - | - | $01c000-$01ffff | 16K | Multiface RAM |
| - | - | $020000-$03ffff | 128K | DivMMC RAM |
| 0-7 | 0-15 | $040000-$05ffff | 128K | Standard 128K RAM |
| 8-15 | 16-31 | $060000-$07ffff | 128K | Extra RAM |
| 16-47 | 32-95 | $080000-$0fffff | 512K | 1st extra IC RAM (available on unexpanded Next) |
| 48-79 | 96-159 | $100000-$17ffff | 512K | 2nd extra IC RAM (only available on expanded Next) |
| 80-111 | 160-223 | $180000-$1fffff | 512K | 3rd extra IC RAM (only available on expanded Next) |
Additionally, the first few pages have certain uses and traits summarised below:
| 16k-banks | 8k-banks | Description |
|---|---|---|
| 0 | 0-1 | Standard RAM, maybe used by EsxDOS. Initially mapped to $c000-$ffff. |
| 1 | 2-3 | Standard RAM, contended on 128, may be used by EsxDOS, RAMdisk on NextZXOS. |
| 2 | 4-5 | Standard RAM. Initially mapped to $8000-$bfff. |
| 3 | 6-7 | Standard RAM, contended on 128, may be used by EsxDOS, RAMdisk on NextZXOS. |
| 4 | 8-9 | Standard RAM, contended on +2/+3, RAMdisk on NextZXOS. |
| 5 | 10-11 | ULA Screen, contended except on Pentagon, cannot be used by NextBASIC commands. Initially mapped to $4000-$7fff. |
| 6 | 12-13 | Standard RAM, contended on +2/+3, RAMdisk on NextZXOS. |
| 7 | 14-15 | ULA Shadow Screen, contended except on Pentagon, NextZXOS Workspace, cannot be used by NextBASIC commands |
| 8 | 16-17 | Next RAM, Default Layer 2, NextZXOS screen and extra data, cannot be used by NextBASIC commands |
| 9-10 | 18-21 | Next RAM, Rest of default Layer 2 |
| 11-13 | 22-27 | Next RAM, Default Layer 2 Shadow Screen |
Please note that NextZXOS moves the Layer 2 bank assignments. Therefore, Layer 2, after NextZXOS boots, is mapped to 16k-banks 9-11 (8k-banks 18-23). The Layer 2 shadow memory is also assigned to 16k-banks 9-11 (8k-banks 18-23).
Z80 Visible Memory map
At start up, the 16-bit address space of the Z80 is mapped to memory as follows:
| Area | 16k-slot | 8k-slot | Default 16k-bank | Default 8k-bank | Description |
|---|---|---|---|---|---|
| $0000-$1fff | 1 | 0 | ROM | ROM (255) | Normally ROM. R/W redirect by Layer 2. IRQ and NMI routines here. |
| $2000-$3fff | 1 | ROM (255) | Normally ROM. R/W redirect by Layer 2. | ||
| $4000-$5fff | 2 | 2 | 5 | 10 | Normally used for normal/shadow ULA screen. |
| $6000-$7fff | 3 | 11 | Timex ULA extended attribute/graphics area. | ||
| $8000-$9fff | 3 | 4 | 2 | 4 | Free RAM. |
| $a000-$bfff | 5 | 5 | Free RAM. | ||
| $c000-$dfff | 4 | 6 | 0 | 0 | Free RAM. Only this area is remappable by 128 memory management. |
| $e000-$ffff | 7 | 1 | Free RAM. Only this area is remappable by 128 memory management. |
Memory decoding order
(check also current VHDL source)
The 0-16k area could be remapped by several different mechanics, the priority order of these (from highest priority to lowest):
- bootrom
- multiface
- divmmc
- layer 2 mapping
- mmu
- config mode
- romcs expansion bus
- rom
The 16k-48k area is either mapped by MMU or overshadowed by Layer2 mapping:
- layer 2 mapping
- mmu
Finally the remaining top 16k, the 48k-64k area is mapped only by MMU.
Paging techniques
128-style memory management
128-style memory management can only alter the bank addressed at $c000 (16k-slot 4, or 8k-slot 7-8). The active 16k-bank at $c000 is selected by writing the 3 LSBs of the 16k-bank number to the bottom 3 bits of Memory Paging Control ($7FFD / 32765), and the 3 MSBs to the bottom 3 bits of Next Memory Bank Select ($DFFD / 57341). (The reason for the division is that the original Spectrum 128, having only 128k of memory, only needed 3 bits.)
On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.
If you are using the standard interrupt handler or OS routines, then any time you write to Memory Paging Control ($7FFD / 32765) you should also store the value at $5B5C. Any time you write to Plus 3 Memory Paging Control ($1FFD / 8189) you should also store the value at $5B67. There is no corresponding system variable for the Next-only Next Memory Bank Select ($DFFD / 57341) and standard OS routines may not support the extended banks properly.
128 Special Paging Mode
"Special paging mode" (also called "AllRam mode" or "CP/M mode") is enabled by writing a value with the LSB set to Plus 3 Memory Paging Control ($1FFD / 8189). Depending on the 3 low bits of this value a memory configuration is selected as follows:
| Bits | Slot 1 | Slot 2 | Slot 3 | Slot 4 |
|---|---|---|---|---|
| %001 | 0 | 1 | 2 | 3 |
| %011 | 4 | 5 | 6 | 7 |
| %101 | 4 | 5 | 6 | 3 |
| %111 | 4 | 7 | 6 | 3 |
Layer 2 Switching
Layer 2 switching can allow one of the 16k-banks to be written to or read from in 16k-slot 1, by writing the 16k-bank number to Layer 2 RAM Page Register ($12) and then enabling Layer 2 paging by setting the paging bits in Layer 2 Access Port ($123B / 4667). You can use also the Layer 2 RAM Shadow Page Register ($13) for the same purpose (change of register $12 is immediately visible at display, while register $13 is not related to display in any way, it works only as bank selector for writing into slot 1). Since core 3.0 you can page not only first 16kiB, but whole 48kiB of Layer 2 to address region $0000..$BFFF).
Writing to/reading from this paging area will then write/read the appropriate area of memory, whereas the other operation may remain unaffected and use the area mapped by other memory management.
Layer 2 is actually 3 banks big, so using Layer 2 controls to access different "sections" of Layer 2 can access the two following banks after the one selected in register $12/$13.
Next Memory Management
The 8k-bank accessed in an 8k-slot is selected by writing the 8k-bank number to bits 7-0 of the 8 Next registers from Memory management slot 0 bank ($50) upwards. $50 addresses 8k-slot 0, $51 addresses 8k-slot 1, and so on.
In addition, in 8k-slots 0 and 1 only, the ROM can be paged in by selecting the otherwise nonexistent 8k-page $FF. Whether the high or the low 8k of the ROM is mapped is determined by which 8k-slot is used.
Interactions between paging methods
In normal mode, changes made in 128 style and Next style memory management are synchronized. The most recent change always has priority. This means that using 128-style memory management to select a new 16k-bank in 16k-slot 4 will update the MMU registers for the two 8k-slots with the corresponding 8k-bank numbers.
However, enabling 128 special paging mode (AllRam mode) mode will override the Next MMU. The bank selections from the AllRam mode table will override the set pages in the Next registers. The MMU registers can still be changed, but they will have no effect until special paging mode is disabled.
Since the 128-style memory management ports are not readable, there is no synchronization applicable in the other direction.
ROM paging and selection
$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.
The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of Memory Paging Control ($7FFD / 32765). The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of Plus 3 Memory Paging Control ($1FFD / 8189). This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.
Paging out ROM
ROM can be paged out by enabling AllRam mode, or by using Next memory management. Beware that some programs may assume that they can find ROM service routines at fixed addresses between $0000-$3fff. More importantly, if the default interrupt mode (IM 1) is set, the Z80 will jump the program counter to $0038 every frame expecting to find an interrupt handler there. If it does not, pain and suffering will likely result. DI is your friend. On the plus side, this does allow you to write your own interrupt handler without the nuisance of using IM 2.
Activating Layer 2's paging will not affect ROM operation, because it only remaps writes, not reads. With core 3.0 you can now enable this paging also for read operation, that will hide ROM data and for example IM 1 interrupt request will execute the data from the Layer 2 bank.
Screen
16k-Bank 5 is the bank read by the ULA to determine what to show on screen. The ULA connects directly to the larger memory space ignoring mapping; the screen is always 16k-Bank 5, no matter where in memory it is (or if it is switched in at all). Setting bit 3 of Memory Paging Control ($7FFD / 32765) will have the ULA read from 16k-bank 7 (the "shadow screen") instead, which can be used as an alternate screen. Beware that this does not map 16k-bank 7 into RAM; to alter 16k-bank 7 it must be mapped by other means.