Difference between revisions of "Video Line Interrupt Control Register"
From SpecNext official Wiki
(Added bit definitions) |
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|ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt. | |ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt. | ||
}} | }} | ||
| + | {| class="wikitable" | ||
| + | ! Bit !! Function | ||
| + | |- | ||
| + | | 7 || (R) INT flag, 1=During INT | ||
| + | |- | ||
| + | | 6-3 || Reserved, must be 0 | ||
| + | |- | ||
| + | | 2 || If 1 disables original ULA interrupt (Reset to 0 after a reset) | ||
| + | |- | ||
| + | | 1 || If 1 enables Line Interrupt (Reset to 0 after a reset) | ||
| + | |- | ||
| + | | 0 || MSB of Line Interrupt line value (Reset to 0 after a reset) | ||
| + | |} | ||
Revision as of 22:48, 20 October 2018
| Number | $22 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Controls the timing of raster interrupts and the ULA frame interrupt. |
| Bit | Function |
|---|---|
| 7 | (R) INT flag, 1=During INT |
| 6-3 | Reserved, must be 0 |
| 2 | If 1 disables original ULA interrupt (Reset to 0 after a reset) |
| 1 | If 1 enables Line Interrupt (Reset to 0 after a reset) |
| 0 | MSB of Line Interrupt line value (Reset to 0 after a reset) |