Video Line Interrupt Control Register: Difference between revisions
From SpecNext Wiki
No edit summary |
Added bit definitions |
||
| Line 5: | Line 5: | ||
|ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt. | |ShortDesc=Controls the timing of raster interrupts and the ULA frame interrupt. | ||
}} | }} | ||
{| class="wikitable" | |||
! Bit !! Function | |||
|- | |||
| 7 || (R) INT flag, 1=During INT | |||
|- | |||
| 6-3 || Reserved, must be 0 | |||
|- | |||
| 2 || If 1 disables original ULA interrupt (Reset to 0 after a reset) | |||
|- | |||
| 1 || If 1 enables Line Interrupt (Reset to 0 after a reset) | |||
|- | |||
| 0 || MSB of Line Interrupt line value (Reset to 0 after a reset) | |||
|} | |||
Revision as of 22:48, 20 October 2018
| Number | TBRegisterNumber::$22 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Controls the timing of raster interrupts and the ULA frame interrupt. |
| Bit | Function |
|---|---|
| 7 | (R) INT flag, 1=During INT |
| 6-3 | Reserved, must be 0 |
| 2 | If 1 disables original ULA interrupt (Reset to 0 after a reset) |
| 1 | If 1 enables Line Interrupt (Reset to 0 after a reset) |
| 0 | MSB of Line Interrupt line value (Reset to 0 after a reset) |