Difference between revisions of "Extended Z80 instruction set"

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(→‎Arithmetic)
Line 5: Line 5:
 
* ''Any 8-bit register'' means A, B, C, D, E, H, and L. F, I and R do not count even though they are technically 8 bit registers. Also, the high and low bytes of IX and IY (IXH, IXL, IYH, IYL) can be used as 8-bit registers although this behavior was undocumented on the original Z80.
 
* ''Any 8-bit register'' means A, B, C, D, E, H, and L. F, I and R do not count even though they are technically 8 bit registers. Also, the high and low bytes of IX and IY (IXH, IXL, IYH, IYL) can be used as 8-bit registers although this behavior was undocumented on the original Z80.
 
* IXY means IX or IY.
 
* IXY means IX or IY.
 +
* Details of ACC32, which appears to be a Next extension, are unknown at present.
 
* For the status field:
 
* For the status field:
 
** S means Standard. It's in the Z80 manual. Everything should support it.
 
** S means Standard. It's in the Z80 manual. Everything should support it.
Line 327: Line 328:
  
 
{{Opcode|opdesc=LD SP, HL
 
{{Opcode|opdesc=LD SP, HL
−
  |ad1=Address
+
  |ad1=Register
 
  |ad2=Register
 
  |ad2=Register
 
  |status=S
 
  |status=S
Line 337: Line 338:
 
  |s=-
 
  |s=-
 
  |tstates=6
 
  |tstates=6
 +
}}
 +
 +
{{Opcode|opdesc=LD HL, SP
 +
|ad1=Register
 +
|ad2=Register
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 
}}
 
}}
  
Line 351: Line 365:
 
  |tstates=10
 
  |tstates=10
 
}}
 
}}
 +
 +
{{Opcode|opdesc=LD ACC32, HLDE
 +
|ad1=Register
 +
|ad2=Register
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
 +
{{Opcode|opdesc=LD HLDE, ACC32
 +
|ad1=Register
 +
|ad2=Register
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
 +
 
|}
 
|}
 
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
 
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
Line 367: Line 409:
 
:* Additionally, SP (only) can be:
 
:* Additionally, SP (only) can be:
 
:** loaded with the contents of HL, IX, or IY.
 
:** loaded with the contents of HL, IX, or IY.
 +
:** (as a Next extended opcode) stored in HL.
 
:* Memory referred to by HL or through IX can be assigned immediate values.
 
:* Memory referred to by HL or through IX can be assigned immediate values.
 +
:* Details of the ACC32 register are unknown at present.
 
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
 
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
 
:LD instructions do not alter any flags unless I or R are loaded into A.
 
:LD instructions do not alter any flags unless I or R are loaded into A.
Line 422: Line 466:
 
  |tstates=23
 
  |tstates=23
 
}}
 
}}
 +
{{Opcode|opdesc=EX ACC32, HLDE
 +
|ad1=Register
 +
|ad2=Register
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
 
|}
 
|}
 
:Exchanges the contents of two sources. The only permitted combinations are
 
:Exchanges the contents of two sources. The only permitted combinations are
Line 474: Line 531:
 
  |tstates=15
 
  |tstates=15
 
}}
 
}}
 +
{{Opcode|opdesc=PUSH nnnn
 +
|ad1=Immediate
 +
|ad2=-
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
 
|}
 
|}
 
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.
 
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.
Line 714: Line 784:
 
:Same as CPIR but loops CPD instead of CPI.  
 
:Same as CPIR but loops CPD instead of CPI.  
  
 +
 +
=== Block Fill ===
 +
;FILLDE (FILL DE bytes)
 +
:{{Opcodelisttop}}
 +
{{Opcode|opdesc=FILLDE
 +
|ad1=-
 +
|ad2=-
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
|}
 +
:Fills DE bytes with the value of A, starting at BC.
  
  
Line 803: Line 891:
 
  |tstates=?
 
  |tstates=?
 
}}
 
}}
−
|}
 
 
{{Opcode|opdesc=ADD HL/DE/BC, nnnn
 
{{Opcode|opdesc=ADD HL/DE/BC, nnnn
 +
|ad1=Register
 +
|ad2=Immediate
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
{{Opcode|opdesc=ADD HLDE, A
 +
|ad1=Register
 +
|ad2=Accumulator
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
{{Opcode|opdesc=ADD HLDE, BC
 +
|ad1=Register
 +
|ad2=Register
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
{{Opcode|opdesc=ADD HLDE, nnnn
 
  |ad1=Register
 
  |ad1=Register
 
  |ad2=Immediate
 
  |ad2=Immediate
Line 944: Line 1,067:
 
  |tstates=19
 
  |tstates=19
 
}}
 
}}
 +
{{Opcode|opdesc=SUB HLDE, A
 +
|ad1=Register
 +
|ad2=Accumulator
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
{{Opcode|opdesc=SUB HLDE, BC
 +
|ad1=Register
 +
|ad2=Register
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
 
|}
 
|}
 
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.  
 
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.  
Line 1,164: Line 1,312:
 
|}
 
|}
 
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.  
 
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.  
 +
 +
 +
 +
;MIRROR
 +
:{{Opcodelisttop}}
 +
{{Opcode|opdesc=MIRROR A
 +
|ad1=Register
 +
|ad2=-
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
{{Opcode|opdesc=MIRROR DE
 +
|ad1=Register
 +
|ad2=-
 +
|status=E
 +
|c=?
 +
|n=?
 +
|pv=?
 +
|h=?
 +
|z=?
 +
|s=?
 +
|tstates=?
 +
}}
 +
|}
 +
:Next extended opcode. Mirrors (reverses the order) of bits in the specified register.
  
  

Revision as of 16:33, 16 August 2017

This is a general list of Z80 instructions with descriptions. For summaries, you can view the Z80 Instruction Table.

Term references

  • Any 8-bit register means A, B, C, D, E, H, and L. F, I and R do not count even though they are technically 8 bit registers. Also, the high and low bytes of IX and IY (IXH, IXL, IYH, IYL) can be used as 8-bit registers although this behavior was undocumented on the original Z80.
  • IXY means IX or IY.
  • Details of ACC32, which appears to be a Next extension, are unknown at present.
  • For the status field:
    • S means Standard. It's in the Z80 manual. Everything should support it.
    • U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
    • E means Extension. It only works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
  • Each of the flag effects is documented as follows:
    • - means the flag is unchanged.
    • 1 or 0 mean the flag is set or reset as appropriate.
    •  ? means we don't know what effect the instruction has on the flag.
    •  ! means the instruction has an unusual effect on the flag which is documented in the description.
    • S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
    • P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it detects the end of a loop (BC reaching 0) as it does for some of the block copy and search instructions.

Register and Data manipulation

LD (LoaD)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
LD r, r' Register Register S - - - - - - 4 {{{shortfx}}}
LD r,n Register Immediate S - - - - - - 7 {{{shortfx}}}
LD r, (HL) Register Indirect S - - - - - - 7 {{{shortfx}}}
LD r, (IXY+d) Register Indexed S - - - - - - 19 {{{shortfx}}}
LD (HL),r Indirect Register S - - - - - - 7 {{{shortfx}}}
LD (IXY+d),r Indexed Register S - - - - - - 19 {{{shortfx}}}
LD (HL), n Indirect Immediate S - - - - - - 10 {{{shortfx}}}
LD (IXY+d), n Indexed Immediate S - - - - - - 19 {{{shortfx}}}
LD A, (BC/DE) Accumulator Indirect S - - - - - - 7 {{{shortfx}}}
LD A, (nn) Accumulator Address S - - - - - - 13 {{{shortfx}}}
LD (BC/DE), A Indirect Accumulator S - - - - - - 7 {{{shortfx}}}
LD (nn), A Address Accumulator S - - - - - - 13 {{{shortfx}}}
LD A, I Accumulator Register S - 0 ! 0 S S 9 {{{shortfx}}}
LD A, R Accumulator Register S - 0 ! 0 S S 9 {{{shortfx}}}
LD I, A Register Accumulator S - - - - - - 9 {{{shortfx}}}
LD R, A Register Accumulator S - - - - - - 9 {{{shortfx}}}
LD BC/DE/HL/SP, nn Register Immediate S - - - - - - 10 {{{shortfx}}}
LD IXY, nn Register Immediate S - - - - - - 14 {{{shortfx}}}
LD HL, (nn) Register Address S - - - - - - 16 {{{shortfx}}}
LD BC/DE/SP/IXY, (nn) Register Address S - - - - - - 20 {{{shortfx}}}
LD (nn), HL Address Register S - - - - - - 16 {{{shortfx}}}
LD (nn), HL Address Register S - - - - - - 16 {{{shortfx}}}
LD (nn), BC/DE/SP/IXY Address Register S - - - - - - 20 {{{shortfx}}}
LD SP, HL Register Register S - - - - - - 6 {{{shortfx}}}
LD HL, SP Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
LD SP, IXY Register Register S - - - - - - 10 {{{shortfx}}}
LD ACC32, HLDE Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
LD HLDE, ACC32 Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
  • Any 8-bit register can be:
    • loaded with an immediate value;
    • loaded with the contents of any other 8-bit register except I and R;
    • loaded with the contents of, or stored in, memory pointed to by HL;
    • loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
  • Additionally, the accumulator A (only) can be:
    • loaded with the contents of, or stored in, memory pointed to by BC or DE;
    • loaded with the contents of, or stored in, memory pointed to by an immediate address;
    • loaded with the contents of I or R.
  • Any 16-bit register pair can be:
    • loaded with an immediate value;
    • loaded with the contents of, or stored in, memory pointed to by an immediate address.
  • Additionally, SP (only) can be:
    • loaded with the contents of HL, IX, or IY.
    • (as a Next extended opcode) stored in HL.
  • Memory referred to by HL or through IX can be assigned immediate values.
  • Details of the ACC32 register are unknown at present.
Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, ld bc, de.
LD instructions do not alter any flags unless I or R are loaded into A.


EX (EXchange)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
EX DE, HL Register Register S - - - - - - 4 {{{shortfx}}}
EX AF, AF' Register Register S ! ! ! ! ! ! 4 {{{shortfx}}}
EX (SP), HL Indirect Register S - - - - - - 19 {{{shortfx}}}
EX (SP), IXY Indirect Register S - - - - - - 23 {{{shortfx}}}
EX ACC32, HLDE Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
Exchanges the contents of two sources. The only permitted combinations are
  • Exchanging DE and HL;
  • Exchanging AF and AF';
  • Exchanging HL, IX, or IY with the contents of memory pointed to by SP.


EXX (EXchange all)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
EXX - - S - - - - - - 4 {{{shortfx}}}
Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.


PUSH
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
PUSH BC/DE/HL/AF Register - S - - - - - - 11 {{{shortfx}}}
PUSH IXY Register - S - - - - - - 15 {{{shortfx}}}
PUSH nnnn Immediate - E ? ? ? ? ? ? ? {{{shortfx}}}
Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.


POP
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
POP BC/DE/HL/AF Register - S - - - - - - 10 {{{shortfx}}}
POP IXY Register - S - - - - - - 14 {{{shortfx}}}
Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.

Block Copy

LDI (LoaD and Increment)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
LDI - - S - 0 L 0 - - 16 {{{shortfx}}}
Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. If BC did not reach 0, P/V is reset, otherwise it is set.


LDIR (LoaD and Increment Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
LDIR - - S - 0 L 0 - - 21x+16 {{{shortfx}}}
Automatically loops LDI until BC reaches zero. Note that no loop occurs with BC=0. Flag effects are the same as LDI except that P/V will always be set, because BC by definition reaches 0 before this instruction ends.


LDD (LoaD and Decrement)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
LDD - - S - 0 L 0 - - 16 {{{shortfx}}}
Same as LDI, but subtracts 1 from DE and HL instead of adding.


LDDR (LoaD and Decrement Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
LDDR - - S - 0 0 0 - - 21 {{{shortfx}}}
Same as LDIR but loops LDD instead of LDI.


LDIX, LDIRX, LDDX, LDDRX
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
LDIX - - E ? ? ? ? ? ? ? {{{shortfx}}}
LDIRX - - E ? ? ? ? ? ? ? {{{shortfx}}}
LDDX - - E ? ? ? ? ? ? ? {{{shortfx}}}
LDDRX - - E ? ? ? ? ? ? ? {{{shortfx}}}
Next-only extended opcodes. Behave the same as their non-X equivalents except the byte is not copied if it is equal to A.


Block Search

CPI (ComPare and Increment)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CPI - - S - 1 L S ! S 16 {{{shortfx}}}
Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. Sets P/V if BC did not reach 0 or resets it if it did.


CPIR (ComPare and Increment Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CPIR - - S - 1 L S ! S 21x+16 {{{shortfx}}}
Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0). Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.


CPD (ComPare and Decrement)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CPD - - S - 1 L S ! S 16 {{{shortfx}}}
Same as CPI, but subtracts 1 from HL instead of adding it.


CPDR (ComPare and Decrement Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CPDR - - S - 1 L S ! S 21x+16 {{{shortfx}}}
Same as CPIR but loops CPD instead of CPI.


Block Fill

FILLDE (FILL DE bytes)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
FILLDE - - E ? ? ? ? ? ? ? {{{shortfx}}}
Fills DE bytes with the value of A, starting at BC.


Arithmetic

ADD
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
ADD A, r Accumulator Register S S 0 V S S S 4 {{{shortfx}}}
ADD A, n Accumulator Immediate S S 0 V S S S 7 {{{shortfx}}}
ADD A, (HL) Accumulator Indirect S S 0 V S S S 7 {{{shortfx}}}
ADD A, (IXY+d) Accumulator Indexed S S 0 V S S S 19 {{{shortfx}}}
ADD HL, BC/DE/HL/SP Register Register S S 0 - ! - - 11 {{{shortfx}}}
ADD IXY, BC/DE/IXY/SP Register Register S S 0 - ! - - 15 {{{shortfx}}}
ADD HL/DE/BC, A Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
ADD HL/DE/BC, nnnn Register Immediate E ? ? ? ? ? ? ? {{{shortfx}}}
ADD HLDE, A Register Accumulator E ? ? ? ? ? ? ? {{{shortfx}}}
ADD HLDE, BC Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
ADD HLDE, nnnn Register Immediate E ? ? ? ? ? ? ? {{{shortfx}}}
Adds values together. Legal combinations are:
  • When adding 8-bit values the first parameter must be A and the second may be:
    • The contents of an 8-bit register;
    • An immediate value;
    • The contents of memory pointed to by HL or by indexing based on IX or IY.
  • When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register.
  • On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A or an immediate value.
For 16 bit additions, H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)


ADC (ADd with Carry)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
ADC A, r Accumulator Register S S 0 V S S S 4 {{{shortfx}}}
ADC A, n Accumulator Immediate S S 0 V S S S 7 {{{shortfx}}}
ADC A, (HL) Accumulator Indirect S S 0 V S S S 7 {{{shortfx}}}
ADC A, (IXY+d) Accumulator Indexed S S 0 V S S S 19 {{{shortfx}}}
ADC HL, BC/DE/HL/SP Register Register S S 0 - ! - - 15 {{{shortfx}}}
Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL.


SUB
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SUB r Register - S S 0 V S S S 4 {{{shortfx}}}
SUB n Immediate - S S 0 V S S S 7 {{{shortfx}}}
SUB (HL) Indirect - S S 0 V S S S 7 {{{shortfx}}}
SUB (IXY+d) Indexed - S S 0 V S S S 19 {{{shortfx}}}
SUB HLDE, A Register Accumulator E ? ? ? ? ? ? ? {{{shortfx}}}
SUB HLDE, BC Register Register E ? ? ? ? ? ? ? {{{shortfx}}}
Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.


SBC (SuBtract with Carry, er, borrow)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SBC A, r Accumulator Register S S 0 V S S S 4 {{{shortfx}}}
SBC A, n Accumulator Immediate S S 0 V S S S 7 {{{shortfx}}}
SBC A, (HL) Accumulator Indirect S S 0 V S S S 7 {{{shortfx}}}
SBC A, (IXY+d) Accumulator Indexed S S 0 V S S S 19 {{{shortfx}}}
SBC HL, BC/DE/HL/SP Register Register S S 0 - ! - - 15 {{{shortfx}}}
Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL.


AND, OR, XOR
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
AND r Register - S 0 0 V 1 S S 4 {{{shortfx}}}
AND n Immediate - S 0 0 V 1 S S 7 {{{shortfx}}}
AND (HL) Indirect - S 0 0 V 1 S S 7 {{{shortfx}}}
AND (IXY+d) Indexed - S 0 0 V 1 S S 19 {{{shortfx}}}
OR r Register - S 0 0 V 0 S S 4 {{{shortfx}}}
OR n Immediate - S 0 0 V 0 S S 7 {{{shortfx}}}
OR (HL) Indirect - S 0 0 V 0 S S 7 {{{shortfx}}}
OR (IXY+d) Indexed - S 0 0 V 0 S S 19 {{{shortfx}}}
XOR r Register - S 0 0 P 0 S S 4 {{{shortfx}}}
XOR n Immediate - S 0 0 P 0 S S 7 {{{shortfx}}}
XOR (HL) Indirect - S 0 0 P 0 S S 7 {{{shortfx}}}
XOR (IXY+d) Indexed - S 0 0 P 0 S S 19 {{{shortfx}}}
Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.


MIRROR
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
MIRROR A Register - E ? ? ? ? ? ? ? {{{shortfx}}}
MIRROR DE Register - E ? ? ? ? ? ? ? {{{shortfx}}}
Next extended opcode. Mirrors (reverses the order) of bits in the specified register.


CP (ComPare)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CP r Register - S S 1 V S S S 4 {{{shortfx}}}
CP n Immediate - S S 1 V S S S 7 {{{shortfx}}}
CP (HL) Indirect - S S 1 V S S S 7 {{{shortfx}}}
CP (IXY+d) Indexed - S S 1 V S S S 19 {{{shortfx}}}
Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
  • CP is not equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.


INC (INCrement)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
INC r Register - S - 0 ! S S S 4 {{{shortfx}}}
INC (HL) Indirect - S - 0 ! S S S 11 {{{shortfx}}}
INC (IXY+d) Indexed - S - 0 ! S S S 23 {{{shortfx}}}
INC BC/DE/HL/SP Register - S - - - - - - 6 {{{shortfx}}}
INC IXY Register - S - - - - - - 10 {{{shortfx}}}
Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
  • INC A is faster than ADD 1.


DEC
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
DEC r Register - S - 1 ! S S S 4 {{{shortfx}}}
DEC (HL) Indirect - S - 1 ! S S S 11 {{{shortfx}}}
DEC (IXY+d) Indexed - S - 1 ! S S S 23 {{{shortfx}}}
DEC BC/DE/HL/SP Register - S - - - - - - 6 {{{shortfx}}}
DEC IXY Register - S - - - - - - 10 {{{shortfx}}}
Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
  • DEC A is faster than SUB 1.


RLC (Rotate Left and Copy)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RLC r Register - S ! 0 P 0 S S 8 {{{shortfx}}}
RLC (HL) Indirect - S ! 0 P 0 S S 15 {{{shortfx}}}
RLC (IXY+d) Indexed - S ! 0 P 0 S S 23 {{{shortfx}}}
RLC r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.


RL (Rotate Left)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RL r Register - S ! 0 P 0 S S 8 {{{shortfx}}}
RL (HL) Indirect - S ! 0 P 0 S S 15 {{{shortfx}}}
RL (IXY+d) Indexed - S ! 0 P 0 S S 23 {{{shortfx}}}
RL r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.


RRC, RR (Rotate Right and Copy, Rotate Right)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RRC r Register - S ! 0 P 0 S S 8 {{{shortfx}}}
RRC (HL) Indirect - S ! 0 P 0 S S 15 {{{shortfx}}}
RRC (IXY+d) Indexed - S ! 0 P 0 S S 23 {{{shortfx}}}
RRC r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
RR r Register - S ! 0 P 0 S S 8 {{{shortfx}}}
RR (HL) Indirect - S ! 0 P 0 S S 15 {{{shortfx}}}
RR (IXY+d) Indexed - S ! 0 P 0 S S 23 {{{shortfx}}}
RR r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
Same as RLC and RL except they rotate right instead of left.


SLA (Shift Left Arithmetic)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SLA r Register - S ! 0 P 0 S S 8 {{{shortfx}}}
SLA (HL) Indirect - S ! 0 P 0 S S 15 {{{shortfx}}}
SLA (IXY+d) Indexed - S ! 0 P 0 S S 23 {{{shortfx}}}
SLA r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
Same as RL except bit 0 is set to zero, not the previous contents of Carry.


SRA (Shift Right Arithmetic)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SRA r Register - S ! 0 P 0 S S 8 {{{shortfx}}}
SRA (HL) Indirect - S ! 0 P 0 S S 15 {{{shortfx}}}
SRA (IXY+d) Indexed - S ! 0 P 0 S S 23 {{{shortfx}}}
SRA r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry.


SRL (Shift Right Logical)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SRL r Register - S ! 0 P 0 S 0 8 {{{shortfx}}}
SRL (HL) Indirect - S ! 0 P 0 S 0 15 {{{shortfx}}}
SRL (IXY+d) Indexed - S ! 0 P 0 S 0 23 {{{shortfx}}}
SRL r,(IX+d) Register Indexed U ! 0 P 0 S 0 ? {{{shortfx}}}
Same as SLA except it shifts right instead of left.


RLCA, RLA, RRCA, RRA
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RLCA - - S ! 0 - 0 - - 4 {{{shortfx}}}
RLA - - S ! 0 - 0 - - 4 {{{shortfx}}}
RRCA - - S ! 0 - 0 - - 4 {{{shortfx}}}
RRA - - S ! 0 - 0 - - 4 {{{shortfx}}}
Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.


SLL (Shift Left Logical)
This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.


SL1 (Shift Left and Add 1)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SL1 r Register - U ! 0 P 0 S S 8 {{{shortfx}}}
SL1 (HL) Indirect - U ! 0 P 0 S S 15 {{{shortfx}}}
SL1 (IXY+d) Indexed - U ! 0 P 0 S S 23 {{{shortfx}}}
SL1 r,(IX+d) Register Indexed U ! 0 P 0 S S ? {{{shortfx}}}
Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.


RLD
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RLD - - S - 0 P 0 S S 18 {{{shortfx}}}
Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.


RRD
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RRD - - S - 0 P 0 S S 18 {{{shortfx}}}
Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.


CPL (ComPLement)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CPL - - S - 1 - 1 - - 4 {{{shortfx}}}
Inverts the contents of the accumulator.


NEG (NEGate)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
NEG - - S ! 1 ! S S S 8 {{{shortfx}}}
Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.


CCF (Craunch Carry Flag)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CCF - - S ! 0 - ! - - 4 {{{shortfx}}}
Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.


SCF (Set Carry Flag)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CCF - - S 1 0 - 0 - - 4 {{{shortfx}}}
Sets the carry flag.


BIT
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
BIT b,r Immediate Register S - 0 ! 1 ! ! 8 {{{shortfx}}}
BIT b,(HL) Immediate Indirect S - 0 ! 1 ! ! 12 {{{shortfx}}}
BIT b,(IXY+d) Immediate Indexed S - 0 ! 1 ! ! 12 {{{shortfx}}}
Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.


SET
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SET b,r Immediate Register S - - - - - - 8 {{{shortfx}}}
SET b,(HL) Immediate Register S - - - - ! ! 15 {{{shortfx}}}
SET b,(IXY+d) Immediate Indexed S - - - - - - 23 {{{shortfx}}}
SET r,b,(IX+d) Immediate Indexed U - - - - - - ? {{{shortfx}}}
Sets the numbered bit on target value. The possible targets are the same as BIT. The final variant is undocumented and stores the result in a register as well as performing the SET.


RES (RESet)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RES b,r Immediate Register S - - - - - - 8 {{{shortfx}}}
RES b,(HL) Immediate Register S - - - - ! ! 15 {{{shortfx}}}
RES b,(IXY+d) Immediate Indexed S - - - - - - 23 {{{shortfx}}}
RES r,b,(IX+d) Immediate Indexed U - - - - - - ? {{{shortfx}}}
Resets the numbered bit on target value. The possible targets are the same as BIT.


DAA (Decimal Adjust Accumulator)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
DAA - - S ! - P ! S S 8 {{{shortfx}}}
Modifies the contents of the accumulator based on the flags and the previous operation to correct for binary coded decimal.


MUL
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
MUL - - E - - - - - - ? {{{shortfx}}}
Next extended opcode. Multiplies HL by DE, leaving the high word of the result in HL and the low word in DE. Does not alter any flags.


SWAPNIB
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
SWAPNIB - - E - - - - - - ? {{{shortfx}}}
Next extended opcode. Swaps the high and low nibbles of the accumulator.

Control Flow

JP (JumP)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
JP nn Address - S - - - - - - 10 {{{shortfx}}}
JP (HL) Register - S - - - - - - 4 {{{shortfx}}}
JP (IXY) Register - S - - - - - - 8 {{{shortfx}}}
Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs look like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to.


JP cc
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
JP Z/NZ/NC/C/PO/PE/P/M, nn Address - S - - - - - - 10 {{{shortfx}}}
Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.


JR (Jump Relative)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
JR nn Immediate - S - - - - - - 12 {{{shortfx}}}
JR C/NC/Z/NZ, nn Immediate - S - - - - - - 12 {{{shortfx}}}
Jumps to an alternate address by adding the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.


DJNZ (Decrement and Jump if Not Zero)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
DJNZ n Immediate - S - - - - - - 13 {{{shortfx}}}
Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.


CALL
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
CALL nn Address - S - - - - - - 17 {{{shortfx}}}
CALL Z/NZ/C/NC/PO/PE/P/M, n Address - S - - - - - - 17 {{{shortfx}}}
Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.
  • If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)


RET
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RET - - S - - - - - - 10 {{{shortfx}}}
RET Z/NZ/C/NC/PO/PE/P/M - - S - - - - - - 11 {{{shortfx}}}
POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.


RETI
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RETI - - S - - - - - - 14 {{{shortfx}}}
Returns from an interrupt service routine.


RETN
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RETN - - S - - - - - - 14 {{{shortfx}}}
Returns from a non-maskable interrupt service routine.


RST (ReSTart)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RST n Immediate - S ? ? ? ? ? ? 11 {{{shortfx}}}
Performs a CALL to a routine located at one of eight fixed locations in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.


NOP (No OPeration)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
NOP - - S - - - - - - 4 {{{shortfx}}}
Does nothing.


HALT
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
HALT - - S - - - - - - 4 {{{shortfx}}}
Suspends the CPU until an interrupt is received.


DI (Disable Interrupts)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
DI - - S - - - - - - 4 {{{shortfx}}}
Disables maskable interrupts.


EI (Enable Interrupts)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
RETN - - S - - - - - - 14 {{{shortfx}}}
Enables maskable interrupts.


IM (Interrupt Mode)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
IM n Immediate - S - - - - - - 8 {{{shortfx}}}
Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)


Input and Output

IN r, (c); OUT (c), r
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
IN r, (c) Register Register S - 0 P 0 S S 12 {{{shortfx}}}
OUT (c),r Register Register S - - - - - - 12 {{{shortfx}}}
Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.


IN (c); OUT (c), 0
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
IN (c) Register - U - 0 P 0 S S ? {{{shortfx}}}
OUT (c),0 Register Immediate U - - - - - - ? {{{shortfx}}}
Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode.


IN a, (n); OUT (n), a
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
IN A, (n) Accumulator Immediate S - - - - - - 11 {{{shortfx}}}
OUT (n),A Immediate Accumulator S - - - - - - 11 {{{shortfx}}}
Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.


INI (INput and Increment)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
INI - - S - 1 ! ! ! ! 16 {{{shortfx}}}
Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; S, H, and P/V are destroyed.


INIR (INput and Increment Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
INIR - - S - 1 ! ! 1 ! 21x+16 {{{shortfx}}}
Loops INIR until B reaches 0. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant.


IND, INDR (INput and Decrement, INput and Decrement Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
IND - - S - 1 ! ! ! ! 16 {{{shortfx}}}
INDR - - S - 1 ! ! 1 ! 21x+16 {{{shortfx}}}
Behave like INI and INIR except that HL is decremented instead of incremented.


OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
OUTI - - S - 1 ! ! ! ! 16 {{{shortfx}}}
OTIR - - S - 1 ! ! 1 ! 21x+16 {{{shortfx}}}
OUTD - - S - 1 ! ! ! ! 16 {{{shortfx}}}
OTDR - - S - 1 ! ! 1 ! 21x+16 {{{shortfx}}}
Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented before the output instead of after.


OUTINB (Out and Increment with No B)
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
OUTINB - - E ? ? ? ? ? ? ? {{{shortfx}}}
Next extended opcode. Behaves like OUTI, but doesn't decrement B.

Undocumented extension opcodes

These opcodes have been mentioned by developers on the project but not documented.

PIXELAD
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
PIXELAD - - E ? ? ? ? ? ? ? {{{shortfx}}}
PIXELDN
Mnemonic Addressing mode 1 Addressing mode 2 Status C N PV H Z S Tstates shortfx
PIXELDN - - E ? ? ? ? ? ? ? {{{shortfx}}}
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