Internal Port Decoding b24-31 Register

Number	$85
Readable	Yes
Writable	Yes
Short Description	Enabling internal ports decoding

Bit	Description
7	(bit 31) (since core3.1.1) re-init all bits 0-31 to 1 upon: 0: hard reset 1: soft reset
6-2	(bit 30-26) Reserved, preserve the current value (or at least use 1)
1	(bit 25) Enabling MB02 DMA Port ($xx0B / 11) (since core3.1.2)
0	(bit 24) Enabling ($BF3B) and ($FF3B) (ULA+)

since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is set OR hard reset and bit 31 is clear (otherwise content is kept intact). All bits are set to 1 upon soft reset.

The internal port decoding enables always apply.

When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

(note: Next registers with number higher than $7F are inaccessible from Copper code)