Internal Port Decoding b8-15 Register

Number	$83
Readable	Yes
Writable	Yes
Short Description	Enabling internal ports decoding

Bit	Description
7	(bit 15) Enabling Layer 2 Access Port ($123B / 4667)
6	(bit 14) Enabling Sprite Attribute Upload ($xx57 / 87), Sprite Pattern Upload ($xx5B / 91) and Sprite Status/Slot Select ($303B / 12347)
5	(bit 13) Enabling Kempston Mouse Buttons ($FADF / 64223), Kempston Mouse X ($FBDF / 64479) and Kempston Mouse Y ($FFDF / 65503)
4	(bit 12) Enabling UART TX ($133B / 4923), UART RX ($143B / 5179) and UART Control ($153B / 5435) (UART)
3	(bit 11) Enabling ($xxE7) and ($xxEB) (SPI)
2	(bit 10) Enabling I2C clock ($103B / 4155) and I2C data ($113B / 4411)
1	(bit 9) Enabling Multiface (two variable ports)
0	(bit 8) Enabling ($xxE3) (DivMMC control)

since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is set OR hard reset and bit 31 is clear (otherwise content is kept intact). All bits are set to 1 upon soft reset.

The internal port decoding enables always apply.

When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

(note: Next registers with number higher than $7F are inaccessible from Copper code)