Internal Port Decoding b0-7 Register

Next Register Number	$82
Readable	Yes
Writable	Yes
Short Description	Enabling internal ports decoding

Bit	Description
7	Enabling $xx37 (also MD2 controller)
6	Enabling $xx1F (also MD1 controller)
5	Enabling $xx6B
4	Enabling +3 floating bus
3	Enabling $1FFD
2	Enabling $DFFD
1	Enabling $7FFD
0	Enabling $xxFF

since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is set OR hard reset and bit 31 is clear (otherwise content is kept intact). All bits are set to 1 upon soft reset.

The internal port decoding enables always apply.

When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

(note: Next registers with number higher than $7F are inaccessible from Copper code)