Extended Z80 instruction set: Difference between revisions

Revision as of 13:15, 7 November 2019

This is a general list of Z80 instructions with descriptions. For summaries, you can view the Z80 Instruction Table. You can also search for opcodes.

Term references

Any 8-bit register means A, B, C, D, E, H, and L. F, I and R do not count even though they are technically 8 bit registers. Also, the high and low bytes of IX and IY (IXH, IXL, IYH, IYL) can be used as 8-bit registers although this behavior was undocumented on the original Z80.
IXY means IX or IY.
For the status field:
- S means Standard. It's in the Z80 manual. Everything should support it.
- U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
- E means Extension. It only works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
Each of the flag effects is documented as follows:
- - means the flag is unchanged.
- 1 or 0 mean the flag is set or reset as appropriate.
- ? means we don't know what effect the instruction has on the flag.
- ! means the instruction has an unusual effect on the flag which is documented in the description.
- S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
- P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it checks BC as loop counter for some of the block copy and search instructions: P/V = (BC != 0)

Register and Data manipulation

LD (LoaD)

{{#subobject:LD r, r' {{#subobject:LD r,n {{#subobject:LD r, (HL) {{#subobject:LD r, (IXY+d) {{#subobject:LD (HL),r {{#subobject:LD (IXY+d),r {{#subobject:LD (HL), n {{#subobject:LD (IXY+d), n {{#subobject:LD A, (BC/DE) {{#subobject:LD A, (nn) {{#subobject:LD (BC/DE), A {{#subobject:LD (nn), A {{#subobject:LD A, I {{#subobject:LD A, R {{#subobject:LD I, A {{#subobject:LD R, A {{#subobject:LD BC/DE/HL/SP, nn {{#subobject:LD IXY, nn {{#subobject:LD HL, (nn) {{#subobject:LD BC/DE/SP/IXY, (nn) {{#subobject:LD (nn), HL {{#subobject:LD (nn), BC/DE/SP/IXY {{#subobject:LD SP, HL {{#subobject:LD SP, IXY

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LD r, r'	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := r'	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=LD r, r'	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := r'	tstates=4 }}	LD r, r'	Register	Register	S	-	-	-	-	-	-	4	r := r'
cleandesc=LD r,n	status=S	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := n	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=LD r,n	status=S	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := n	tstates=7 }}	LD r,n	Register	Immediate	S	-	-	-	-	-	-	7	r := n
cleandesc=LD r, (HL)	status=S	isZ80Instruction=y	admode1=Register	admode2=Indirect	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := HL*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=LD r, (HL)	status=S	isZ80Instruction=y	admode1=Register	admode2=Indirect	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := HL*	tstates=7 }}	LD r, (HL)	Register	Indirect	S	-	-	-	-	-	-	7	r := HL*
cleandesc=LD r, (IXY+d)	status=S	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := (IXY+d)*	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=LD r, (IXY+d)	status=S	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r := (IXY+d)*	tstates=19 }}	LD r, (IXY+d)	Register	Indexed	S	-	-	-	-	-	-	19	r := (IXY+d)*
cleandesc=LD (HL),r	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL* := r	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=LD (HL),r	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL* := r	tstates=7 }}	LD (HL),r	Indirect	Register	S	-	-	-	-	-	-	7	HL* := r
cleandesc=LD (IXY+d),r	status=S	isZ80Instruction=y	admode1=Indexed	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+D)* := r	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=LD (IXY+d),r	status=S	isZ80Instruction=y	admode1=Indexed	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+D)* := r	tstates=19 }}	LD (IXY+d),r	Indexed	Register	S	-	-	-	-	-	-	19	(IXY+D)* := r
cleandesc=LD (HL), n	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL* := n	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=LD (HL), n	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL* := n	tstates=10 }}	LD (HL), n	Indirect	Immediate	S	-	-	-	-	-	-	10	HL* := n
cleandesc=LD (IXY+d), n	status=S	isZ80Instruction=y	admode1=Indexed	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+d)* := n	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=LD (IXY+d), n	status=S	isZ80Instruction=y	admode1=Indexed	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+d)* := n	tstates=19 }}	LD (IXY+d), n	Indexed	Immediate	S	-	-	-	-	-	-	19	(IXY+d)* := n
cleandesc=LD A, (BC/DE)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A := rr*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=LD A, (BC/DE)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A := rr*	tstates=7 }}	LD A, (BC/DE)	Accumulator	Indirect	S	-	-	-	-	-	-	7	A := rr*
cleandesc=LD A, (nn)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Address	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A := (nn)*	tstates=13 }} {{#cargo_store: _table = Opcode	cleandesc=LD A, (nn)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Address	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A := (nn)*	tstates=13 }}	LD A, (nn)	Accumulator	Address	S	-	-	-	-	-	-	13	A := (nn)*
cleandesc=LD (BC/DE), A	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr* := A	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=LD (BC/DE), A	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr* := A	tstates=7 }}	LD (BC/DE), A	Indirect	Accumulator	S	-	-	-	-	-	-	7	rr* := A
cleandesc=LD (nn), A	status=S	isZ80Instruction=y	admode1=Address	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(nn)* := A	tstates=13 }} {{#cargo_store: _table = Opcode	cleandesc=LD (nn), A	status=S	isZ80Instruction=y	admode1=Address	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(nn)* := A	tstates=13 }}	LD (nn), A	Address	Accumulator	S	-	-	-	-	-	-	13	(nn)* := A
cleandesc=LD A, I	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=-	neffect=0	pveffect=!	heffect=0	zeffect=S	seffect=S	shortfx=A := I; P/V:=IFF2	tstates=9 }} {{#cargo_store: _table = Opcode	cleandesc=LD A, I	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=-	neffect=0	pveffect=!	heffect=0	zeffect=S	seffect=S	shortfx=A := I; P/V:=IFF2	tstates=9 }}	LD A, I	Accumulator	Register	S	-	0	!	0	S	S	9	A := I; P/V:=IFF2
cleandesc=LD A, R	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=-	neffect=0	pveffect=!	heffect=0	zeffect=S	seffect=S	shortfx=A := R; P/V:=IFF2	tstates=9 }} {{#cargo_store: _table = Opcode	cleandesc=LD A, R	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=-	neffect=0	pveffect=!	heffect=0	zeffect=S	seffect=S	shortfx=A := R; P/V:=IFF2	tstates=9 }}	LD A, R	Accumulator	Register	S	-	0	!	0	S	S	9	A := R; P/V:=IFF2
cleandesc=LD I, A	status=S	isZ80Instruction=y	admode1=Register	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=I := A	tstates=9 }} {{#cargo_store: _table = Opcode	cleandesc=LD I, A	status=S	isZ80Instruction=y	admode1=Register	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=I := A	tstates=9 }}	LD I, A	Register	Accumulator	S	-	-	-	-	-	-	9	I := A
cleandesc=LD R, A	status=S	isZ80Instruction=y	admode1=Register	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=R := A	tstates=9 }} {{#cargo_store: _table = Opcode	cleandesc=LD R, A	status=S	isZ80Instruction=y	admode1=Register	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=R := A	tstates=9 }}	LD R, A	Register	Accumulator	S	-	-	-	-	-	-	9	R := A
cleandesc=LD BC/DE/HL/SP, nn	status=S	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr := nn	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=LD BC/DE/HL/SP, nn	status=S	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr := nn	tstates=10 }}	LD BC/DE/HL/SP, nn	Register	Immediate	S	-	-	-	-	-	-	10	rr := nn
cleandesc=LD IXY, nn	status=S	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr := nn	tstates=14 }} {{#cargo_store: _table = Opcode	cleandesc=LD IXY, nn	status=S	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr := nn	tstates=14 }}	LD IXY, nn	Register	Immediate	S	-	-	-	-	-	-	14	rr := nn
cleandesc=LD HL, (nn)	status=S	isZ80Instruction=y	admode1=Register	admode2=Address	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL := (nn)*	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=LD HL, (nn)	status=S	isZ80Instruction=y	admode1=Register	admode2=Address	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL := (nn)*	tstates=16 }}	LD HL, (nn)	Register	Address	S	-	-	-	-	-	-	16	HL := (nn)*
cleandesc=LD BC/DE/SP/IXY, (nn)	status=S	isZ80Instruction=y	admode1=Register	admode2=Address	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr := (nn)*	tstates=20 }} {{#cargo_store: _table = Opcode	cleandesc=LD BC/DE/SP/IXY, (nn)	status=S	isZ80Instruction=y	admode1=Register	admode2=Address	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr := (nn)*	tstates=20 }}	LD BC/DE/SP/IXY, (nn)	Register	Address	S	-	-	-	-	-	-	20	rr := (nn)*
cleandesc=LD (nn), HL	status=S	isZ80Instruction=y	admode1=Address	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(nn)* := HL	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=LD (nn), HL	status=S	isZ80Instruction=y	admode1=Address	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(nn)* := HL	tstates=16 }}	LD (nn), HL	Address	Register	S	-	-	-	-	-	-	16	(nn)* := HL
cleandesc=LD (nn), BC/DE/SP/IXY	status=S	isZ80Instruction=y	admode1=Address	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(nn)* := rr	tstates=20 }} {{#cargo_store: _table = Opcode	cleandesc=LD (nn), BC/DE/SP/IXY	status=S	isZ80Instruction=y	admode1=Address	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(nn)* := rr	tstates=20 }}	LD (nn), BC/DE/SP/IXY	Address	Register	S	-	-	-	-	-	-	20	(nn)* := rr
cleandesc=LD SP, HL	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP := HL	tstates=6 }} {{#cargo_store: _table = Opcode	cleandesc=LD SP, HL	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP := HL	tstates=6 }}	LD SP, HL	Register	Register	S	-	-	-	-	-	-	6	SP := HL
cleandesc=LD SP, IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP := IXY	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=LD SP, IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP := IXY	tstates=10 }}	LD SP, IXY	Register	Register	S	-	-	-	-	-	-	10	SP := IXY

The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:

Any 8-bit register can be:
- loaded with an immediate value;
- loaded with the contents of any other 8-bit register except I and R;
- loaded with the contents of, or stored in, memory pointed to by HL;
- loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
Additionally, the accumulator A (only) can be:
- loaded with the contents of, or stored in, memory pointed to by BC or DE;
- loaded with the contents of, or stored in, memory pointed to by an immediate address;
- loaded with the contents of I or R.
Any 16-bit register pair can be:
- loaded with an immediate value;
- loaded with the contents of, or stored in, memory pointed to by an immediate address.
Additionally, SP (only) can be:
- loaded with the contents of HL, IX, or IY.
- The planned ld hl, sp didn't make it to Next yet, one possible workaround is: ld hl,0; add hl,sp;
Memory referred to by HL or through IX can be assigned immediate values.

Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, ld bc, de.

LD instructions do not alter any flags unless I or R are loaded into A.

EX (EXchange)

{{#subobject:EX DE, HL {{#subobject:EX AF, AF' {{#subobject:EX (SP), HL {{#subobject:EX (SP), IXY

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=EX DE, HL	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(DE,HL)	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=EX DE, HL	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(DE,HL)	tstates=4 }}	EX DE, HL	Register	Register	S	-	-	-	-	-	-	4	swap(DE,HL)
cleandesc=EX AF, AF'	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=!	neffect=!	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=swap(AF,AF')	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=EX AF, AF'	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=!	neffect=!	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=swap(AF,AF')	tstates=4 }}	EX AF, AF'	Register	Register	S	!	!	!	!	!	!	4	swap(AF,AF')
cleandesc=EX (SP), HL	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(SP*,HL)	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=EX (SP), HL	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(SP*,HL)	tstates=19 }}	EX (SP), HL	Indirect	Register	S	-	-	-	-	-	-	19	swap(SP*,HL)
cleandesc=EX (SP), IXY	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(SP*,IXY)	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=EX (SP), IXY	status=S	isZ80Instruction=y	admode1=Indirect	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(SP*,IXY)	tstates=23 }}	EX (SP), IXY	Indirect	Register	S	-	-	-	-	-	-	23	swap(SP*,IXY)

Exchanges the contents of two sources. The only permitted combinations are

Exchanging DE and HL;
Exchanging AF and AF';
Exchanging HL, IX, or IY with the contents of memory pointed to by SP.

EXX (EXchange all)

{{#subobject:EXX

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=EXX	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(BC,BC');swap(DE,DE');swap(HL,HL')	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=EXX	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=swap(BC,BC');swap(DE,DE');swap(HL,HL')	tstates=4 }}	EXX	-	-	S	-	-	-	-	-	-	4	swap(BC,BC');swap(DE,DE');swap(HL,HL')

Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged.

PUSH

{{#subobject:PUSH BC/DE/HL/AF {{#subobject:PUSH IXY {{#subobject:PUSH nnnn

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=PUSH BC/DE/HL/AF	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=rr	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=PUSH BC/DE/HL/AF	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=rr	tstates=11 }}	PUSH BC/DE/HL/AF	Register	-	S	-	-	-	-	-	-	11	SP-=2; SP*:=rr
cleandesc=PUSH IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=rr	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=PUSH IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=rr	tstates=15 }}	PUSH IXY	Register	-	S	-	-	-	-	-	-	15	SP-=2; SP*:=rr
cleandesc=PUSH nnnn	status=E	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=nnnn	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=PUSH nnnn	status=E	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=nnnn	tstates=23 }}	PUSH nnnn	Immediate	-	E	-	-	-	-	-	-	23	SP-=2; SP*:=nnnn

Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.

POP

{{#subobject:POP BC/DE/HL {{#subobject:POP AF {{#subobject:POP IXY

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=POP BC/DE/HL	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr:=SP*; SP+=2	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=POP BC/DE/HL	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr:=SP*; SP+=2	tstates=10 }}	POP BC/DE/HL	Register	-	S	-	-	-	-	-	-	10	rr:=SP*; SP+=2
cleandesc=POP AF	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=!	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=rr:=SP*; SP+=2	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=POP AF	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=!	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=rr:=SP*; SP+=2	tstates=10 }}	POP AF	Register	-	S	!	!	!	!	!	!	10	rr:=SP*; SP+=2
cleandesc=POP IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr:=SP*; SP+=2	tstates=14 }} {{#cargo_store: _table = Opcode	cleandesc=POP IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr:=SP*; SP+=2	tstates=14 }}	POP IXY	Register	-	S	-	-	-	-	-	-	14	rr:=SP*; SP+=2

Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.

Popping into AF does set value of flag register F directly to low 8 bits of value from stack.

Block Copy

LDI (LoaD and Increment)

{{#subobject:LDI

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=L	heffect=0	zeffect=-	seffect=-	shortfx=DE:=HL; DE++; HL++; BC--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=LDI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=L	heffect=0	zeffect=-	seffect=-	shortfx=DE:=HL; DE++; HL++; BC--	tstates=16 }}	LDI	-	-	S	-	0	L	0	-	-	16	DE:=HL; DE++; HL++; BC--

Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

LDIR (LoaD and Increment Repeated)

{{#subobject:LDIR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=L	heffect=0	zeffect=-	seffect=-	shortfx=do LDI while(BC>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=LDIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=L	heffect=0	zeffect=-	seffect=-	shortfx=do LDI while(BC>0)	tstates=21x+16 }}	LDIR	-	-	S	-	0	L	0	-	-	21x+16	do LDI while(BC>0)

Automatically loops LDI until BC reaches zero. Note the last iteration starts when BC=1 and ends with BC=0 (starting the LDIR with BC=0 will start 64kiB transfer, most likely overwriting vital parts of system memory and/or code itself).

Flag effects are the same as LDI except that P/V will always be reset, because BC by definition reaches 0 before this instruction ends (normally - unless something overwrites LDIR opcode while BC>0).

Interrupts may interrupt LDIR instruction while looping (after each single LDI sub-part finished) and LDIR will resume after and finish loop properly.

LDD (LoaD and Decrement)

{{#subobject:LDD

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=L	heffect=0	zeffect=-	seffect=-	shortfx=DE:=HL; DE--; HL--; BC--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=LDD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=L	heffect=0	zeffect=-	seffect=-	shortfx=DE:=HL; DE--; HL--; BC--	tstates=16 }}	LDD	-	-	S	-	0	L	0	-	-	16	DE:=HL; DE--; HL--; BC--

Same as LDI, but subtracts 1 from DE and HL instead of adding.

LDDR (LoaD and Decrement Repeated)

{{#subobject:LDDR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=0	heffect=0	zeffect=-	seffect=-	shortfx=do LDD while(BC>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=LDDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=0	heffect=0	zeffect=-	seffect=-	shortfx=do LDD while(BC>0)	tstates=21x+16 }}	LDDR	-	-	S	-	0	0	0	-	-	21x+16	do LDD while(BC>0)

Same as LDIR but loops LDD instead of LDI.

LDWS

{{#subobject:LDWS

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDWS	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=DE:=HL; INC L; INC D;	tstates=14 }} {{#cargo_store: _table = Opcode	cleandesc=LDWS	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=DE:=HL; INC L; INC D;	tstates=14 }}	LDWS	-	-	E	-	0	!	S	S	S	14	DE:=HL; INC L; INC D;

Next-only extended opcode. Copies the byte pointed to by HL to the address pointed to by DE and increments only L and D. This is used for vertically copying bytes to the Layer 2 display.

The flags are identical to what the INC D instruction would produce.

Note the source data are read only from single 256B (aligned) block of memory, because only L is incremented, not HL.

LDIX, LDIRX, LDDX, LDDRX

{{#subobject:LDIX {{#subobject:LDIRX {{#subobject:LDDX {{#subobject:LDDRX

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDIX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx={if HL!=A DE:=HL*;} DE++; HL++; BC--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=LDIX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx={if HL!=A DE:=HL*;} DE++; HL++; BC--	tstates=16 }}	LDIX	-	-	E	-	-	-	-	-	-	16	{if HL!=A DE:=HL*;} DE++; HL++; BC--
cleandesc=LDIRX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=do LDIX while(BC>0)	tstates=21/16 }} {{#cargo_store: _table = Opcode	cleandesc=LDIRX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=do LDIX while(BC>0)	tstates=21/16 }}	LDIRX	-	-	E	-	-	-	-	-	-	21/16	do LDIX while(BC>0)
cleandesc=LDDX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx={if HL!=A DE:=HL*;} DE++; HL--; BC--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=LDDX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx={if HL!=A DE:=HL*;} DE++; HL--; BC--	tstates=16 }}	LDDX	-	-	E	-	-	-	-	-	-	16	{if HL!=A DE:=HL*;} DE++; HL--; BC--
cleandesc=LDDRX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=do LDDX while(BC>0)	tstates=21/16 }} {{#cargo_store: _table = Opcode	cleandesc=LDDRX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=do LDDX while(BC>0)	tstates=21/16 }}	LDDRX	-	-	E	-	-	-	-	-	-	21/16	do LDDX while(BC>0)

Next-only extended opcodes. Behave similarly as their non-X equivalents except the byte is not copied if it is equal to A and LDDX/LDDRX advance DE by incrementing it (like LDI), while HL is decremented (like LDD).

Second difference to non-X instructions (as usual with next-only opcodes due to implementation), the extended ones don't modify any flags.

LDPIRX

{{#subobject:LDPIRX

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=LDPIRX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=do{t:=(HL&$FFF8+E&7); {if t!=A DE:=t;} DE++; BC--}while(BC>0)	tstates=21/16 }} {{#cargo_store: _table = Opcode	cleandesc=LDPIRX	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=do{t:=(HL&$FFF8+E&7); {if t!=A DE:=t;} DE++; BC--}while(BC>0)	tstates=21/16 }}	LDPIRX	-	-	E	-	-	-	-	-	-	21/16	do{t:=(HL&$FFF8+E&7); {if t!=A DE:=t;} DE++; BC--}while(BC>0)

Similar to LDIRX except the source byte address is not just HL, but is obtained by using the top 13 bits of HL and the lower 3 bits of DE and HL does not increment during whole loop (HL works as base address of aligned 8 byte lookup table, DE works as destination and also wrapping index 0..7 into table). This is intended for "pattern fill" functionality.

Block Search

CPI (ComPare and Increment)

{{#subobject:CPI

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CPI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=HL*==A?; HL++; BC--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=CPI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=HL*==A?; HL++; BC--	tstates=16 }}	CPI	-	-	S	-	1	L	S	!	S	16	HL*==A?; HL++; BC--

Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. P/V is set to (BC!=0), i.e. set when non zero.

CPIR (ComPare and Increment Repeated)

{{#subobject:CPIR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CPIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=do CPI while (!Z && BC>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=CPIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=do CPI while (!Z && BC>0)	tstates=21x+16 }}	CPIR	-	-	S	-	1	L	S	!	S	21x+16	do CPI while (!Z && BC>0)

Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0).

Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.

CPD (ComPare and Decrement)

{{#subobject:CPD

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CPD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=HL*==A?; HL--; BC--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=CPD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=HL*==A?; HL--; BC--	tstates=16 }}	CPD	-	-	S	-	1	L	S	!	S	16	HL*==A?; HL--; BC--

Same as CPI, but subtracts 1 from HL instead of adding it.

CPDR (ComPare and Decrement Repeated)

{{#subobject:CPDR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CPDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=do CPD while (!Z && BC>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=CPDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=L	heffect=S	zeffect=!	seffect=S	shortfx=do CPD while (!Z && BC>0)	tstates=21x+16 }}	CPDR	-	-	S	-	1	L	S	!	S	21x+16	do CPD while (!Z && BC>0)

Same as CPIR but loops CPD instead of CPI.

Arithmetic

ADD

{{#subobject:ADD A, r {{#subobject:ADD A, n {{#subobject:ADD A, (HL) {{#subobject:ADD A, (IXY+d) {{#subobject:ADD HL, BC/DE/HL/SP {{#subobject:ADD IXY, BC/DE/IXY/SP {{#subobject:ADD HL/DE/BC, A {{#subobject:ADD HL/DE/BC, nnnn

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=ADD A, r	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=r	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=ADD A, r	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=r	tstates=4 }}	ADD A, r	Accumulator	Register	S	S	0	V	S	S	S	4	A+=r
cleandesc=ADD A, n	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=n	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=ADD A, n	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=n	tstates=7 }}	ADD A, n	Accumulator	Immediate	S	S	0	V	S	S	S	7	A+=n
cleandesc=ADD A, (HL)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=HL*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=ADD A, (HL)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=HL*	tstates=7 }}	ADD A, (HL)	Accumulator	Indirect	S	S	0	V	S	S	S	7	A+=HL*
cleandesc=ADD A, (IXY+d)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indexed	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=(IXY+d)*	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=ADD A, (IXY+d)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indexed	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=(IXY+d)*	tstates=19 }}	ADD A, (IXY+d)	Accumulator	Indexed	S	S	0	V	S	S	S	19	A+=(IXY+d)*
cleandesc=ADD HL, BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=0	pveffect=-	heffect=!	zeffect=-	seffect=-	shortfx=HL+=rr	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=ADD HL, BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=0	pveffect=-	heffect=!	zeffect=-	seffect=-	shortfx=HL+=rr	tstates=11 }}	ADD HL, BC/DE/HL/SP	Register	Register	S	S	0	-	!	-	-	11	HL+=rr
cleandesc=ADD IXY, BC/DE/IXY/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=0	pveffect=-	heffect=!	zeffect=-	seffect=-	shortfx=IXY+=rr	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=ADD IXY, BC/DE/IXY/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=0	pveffect=-	heffect=!	zeffect=-	seffect=-	shortfx=IXY+=rr	tstates=15 }}	ADD IXY, BC/DE/IXY/SP	Register	Register	S	S	0	-	!	-	-	15	IXY+=rr
cleandesc=ADD HL/DE/BC, A	status=E	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr+=unsigned A	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=ADD HL/DE/BC, A	status=E	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr+=unsigned A	tstates=8 }}	ADD HL/DE/BC, A	Register	Register	E	-	-	-	-	-	-	8	rr+=unsigned A
cleandesc=ADD HL/DE/BC, nnnn	status=E	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=?	neffect=?	pveffect=?	heffect=?	zeffect=?	seffect=?	shortfx=rr+=nnnn	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=ADD HL/DE/BC, nnnn	status=E	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=?	neffect=?	pveffect=?	heffect=?	zeffect=?	seffect=?	shortfx=rr+=nnnn	tstates=16 }}	ADD HL/DE/BC, nnnn	Register	Immediate	E	?	?	?	?	?	?	16	rr+=nnnn

Adds values together. Legal combinations are:

When adding 8-bit values the first parameter must be A and the second may be:
- The contents of an 8-bit register;
- An immediate value;
- The contents of memory pointed to by HL or by indexing based on IX or IY.
When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register.
For 16 bit additions (regular Z80), H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)
On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A (A will be zero extended to 16 bits) or an immediate value. It's not yet clear if the Next-extended ADD rr,nnnn will preserve or modify flags (the ADD rr,A keeps flags intact).

ADC (ADd with Carry)

{{#subobject:ADC A, r {{#subobject:ADC A, n {{#subobject:ADC A, (HL) {{#subobject:ADC A, (IXY+d) {{#subobject:ADC HL, BC/DE/HL/SP

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=ADC A, r	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=r+(CF?1:0)	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=ADC A, r	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=r+(CF?1:0)	tstates=4 }}	ADC A, r	Accumulator	Register	S	S	V	S	S	S	4	A+=r+(CF?1:0)
cleandesc=ADC A, n	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=n+(CF?1:0)	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=ADC A, n	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=n+(CF?1:0)	tstates=7 }}	ADC A, n	Accumulator	Immediate	S	S	V	S	S	S	7	A+=n+(CF?1:0)
cleandesc=ADC A, (HL)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=HL*+(CF?1:0)	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=ADC A, (HL)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=HL*+(CF?1:0)	tstates=7 }}	ADC A, (HL)	Accumulator	Indirect	S	S	V	S	S	S	7	A+=HL*+(CF?1:0)
cleandesc=ADC A, (IXY+d)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indexed	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=(IXY+d)*+(CF?1:0)	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=ADC A, (IXY+d)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indexed	ceffect=S	neffect=0	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A+=(IXY+d)*+(CF?1:0)	tstates=19 }}	ADC A, (IXY+d)	Accumulator	Indexed	S	S	V	S	S	S	19	A+=(IXY+d)*+(CF?1:0)
cleandesc=ADC HL, BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=0	pveffect=V	heffect=!	zeffect=S	seffect=S	shortfx=HL+=rr+(CF?1:0)	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=ADC HL, BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=0	pveffect=V	heffect=!	zeffect=S	seffect=S	shortfx=HL+=rr+(CF?1:0)	tstates=15 }}	ADC HL, BC/DE/HL/SP	Register	Register	S	S	V	!	S	S	15	HL+=rr+(CF?1:0)

Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if carry from bit 11; otherwise, it is reset.

SUB

{{#subobject:SUB r {{#subobject:SUB n {{#subobject:SUB (HL) {{#subobject:SUB (IXY+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SUB r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= r	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=SUB r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= r	tstates=4 }}	SUB r	Register	-	S	S	1	V	S	S	S	4	A -= r
cleandesc=SUB n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= n	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=SUB n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= n	tstates=7 }}	SUB n	Immediate	-	S	S	1	V	S	S	S	7	A -= n
cleandesc=SUB (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= HL*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=SUB (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= HL*	tstates=7 }}	SUB (HL)	Indirect	-	S	S	1	V	S	S	S	7	A -= HL*
cleandesc=SUB (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= (IXY+d)*	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=SUB (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A -= (IXY+d)*	tstates=19 }}	SUB (IXY+d)	Indexed	-	S	S	1	V	S	S	S	19	A -= (IXY+d)*

Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers.

SBC (SuBtract with Carry, er, borrow)

{{#subobject:SBC A, r {{#subobject:SBC A, n {{#subobject:SBC A, (HL) {{#subobject:SBC A, (IXY+d) {{#subobject:SBC HL, BC/DE/HL/SP

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SBC A, r	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(r+(CF?1:0))	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=SBC A, r	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Register	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(r+(CF?1:0))	tstates=4 }}	SBC A, r	Accumulator	Register	S	S	1	V	S	S	S	4	A-=(r+(CF?1:0))
cleandesc=SBC A, n	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(n+(CF?1:0))	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=SBC A, n	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(n+(CF?1:0))	tstates=7 }}	SBC A, n	Accumulator	Immediate	S	S	1	V	S	S	S	7	A-=(n+(CF?1:0))
cleandesc=SBC A, (HL)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(HL*+(CF?1:0))	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=SBC A, (HL)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indirect	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(HL*+(CF?1:0))	tstates=7 }}	SBC A, (HL)	Accumulator	Indirect	S	S	1	V	S	S	S	7	A-=(HL*+(CF?1:0))
cleandesc=SBC A, (IXY+d)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indexed	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=((IXY+d)+(CF?1:0))	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=SBC A, (IXY+d)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Indexed	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=((IXY+d)+(CF?1:0))	tstates=19 }}	SBC A, (IXY+d)	Accumulator	Indexed	S	S	1	V	S	S	S	19	A-=((IXY+d)+(CF?1:0))
cleandesc=SBC HL, BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=1	pveffect=V	heffect=!	zeffect=S	seffect=S	shortfx=HL-=(rr+(CF?1:0))	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=SBC HL, BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=S	neffect=1	pveffect=V	heffect=!	zeffect=S	seffect=S	shortfx=HL-=(rr+(CF?1:0))	tstates=15 }}	SBC HL, BC/DE/HL/SP	Register	Register	S	S	1	V	!	S	S	15	HL-=(rr+(CF?1:0))

Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. For 16-bit values the H flag is set if borrow from bit 12; otherwise, it is reset.

AND, OR, XOR

{{#subobject:AND r {{#subobject:AND n {{#subobject:AND (HL) {{#subobject:AND (IXY+d) {{#subobject:OR r {{#subobject:OR n {{#subobject:OR (HL) {{#subobject:OR (IXY+d) {{#subobject:XOR r {{#subobject:XOR n {{#subobject:XOR (HL) {{#subobject:XOR (IXY+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=AND r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & r	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=AND r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & r	tstates=4 }}	AND r	Register	-	S	V	1	S	S	4	A := A & r
cleandesc=AND n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & n	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=AND n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & n	tstates=7 }}	AND n	Immediate	-	S	V	1	S	S	7	A := A & n
cleandesc=AND (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & HL*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=AND (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & HL*	tstates=7 }}	AND (HL)	Indirect	-	S	V	1	S	S	7	A := A & HL*
cleandesc=AND (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & (IXY+d)*	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=AND (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=1	zeffect=S	seffect=S	shortfx=A := A & (IXY+d)*	tstates=19 }}	AND (IXY+d)	Indexed	-	S	V	1	S	S	19	A := A & (IXY+d)*
cleandesc=OR r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR r	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=OR r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR r	tstates=4 }}	OR r	Register	-	S	V	0	S	S	4	A := A OR r
cleandesc=OR n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR n	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=OR n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR n	tstates=7 }}	OR n	Immediate	-	S	V	0	S	S	7	A := A OR n
cleandesc=OR (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR HL*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=OR (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR HL*	tstates=7 }}	OR (HL)	Indirect	-	S	V	0	S	S	7	A := A OR HL*
cleandesc=OR (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR (IXY+d)*	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=OR (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=0	neffect=0	pveffect=V	heffect=0	zeffect=S	seffect=S	shortfx=A := A OR (IXY+d)*	tstates=19 }}	OR (IXY+d)	Indexed	-	S	V	0	S	S	19	A := A OR (IXY+d)*
cleandesc=XOR r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ r	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=XOR r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ r	tstates=4 }}	XOR r	Register	-	S	P	0	S	S	4	A := A ^ r
cleandesc=XOR n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ n	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=XOR n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ n	tstates=7 }}	XOR n	Immediate	-	S	P	0	S	S	7	A := A ^ n
cleandesc=XOR (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ HL*	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=XOR (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ HL*	tstates=7 }}	XOR (HL)	Indirect	-	S	P	0	S	S	7	A := A ^ HL*
cleandesc=XOR (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ (IXY+d)*	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=XOR (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=0	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=A := A ^ (IXY+d)*	tstates=19 }}	XOR (IXY+d)	Indexed	-	S	P	0	S	S	19	A := A ^ (IXY+d)*

Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB.

XOR A is faster and shorter than LD A,0

MIRROR

{{#subobject:MIRROR A

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=MIRROR A	status=E	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A[76543210]:=A[01234567]	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=MIRROR A	status=E	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A[76543210]:=A[01234567]	tstates=8 }}	MIRROR A	Register	-	E	-	-	-	-	-	-	8	A[76543210]:=A[01234567]

Next extended opcode. Mirrors (reverses the order) of bits in the accumulator. Older core versions supported MIRROR DE, but this was removed.

CP (ComPare)

{{#subobject:CP r {{#subobject:CP n {{#subobject:CP (HL) {{#subobject:CP (IXY+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CP r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=r?	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=CP r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=r?	tstates=4 }}	CP r	Register	-	S	S	1	V	S	S	S	4	A-=r?
cleandesc=CP n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=n?	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=CP n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=n?	tstates=7 }}	CP n	Immediate	-	S	S	1	V	S	S	S	7	A-=n?
cleandesc=CP (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=HL*?	tstates=7 }} {{#cargo_store: _table = Opcode	cleandesc=CP (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=HL*?	tstates=7 }}	CP (HL)	Indirect	-	S	S	1	V	S	S	S	7	A-=HL*?
cleandesc=CP (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(IXY+d)?	tstates=19 }} {{#cargo_store: _table = Opcode	cleandesc=CP (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=S	neffect=1	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A-=(IXY+d)?	tstates=19 }}	CP (IXY+d)	Indexed	-	S	S	1	V	S	S	S	19	A-=(IXY+d)?

Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.

CP is not equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.

TEST

{{#subobject:TEST n

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=TEST n	status=E	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=S	neffect=?	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A&n?	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=TEST n	status=E	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=S	neffect=?	pveffect=V	heffect=S	zeffect=S	seffect=S	shortfx=A&n?	tstates=11 }}	TEST n	Immediate	-	E	S	?	V	S	S	S	11	A&n?

Next extended opcode. Similar to CP, but performs an AND instead of a subtraction.

INC (INCrement)

{{#subobject:INC r {{#subobject:INC (HL) {{#subobject:INC (IXY+d) {{#subobject:INC BC/DE/HL/SP {{#subobject:INC IXY

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=INC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=r++	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=INC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=r++	tstates=4 }}	INC r	Register	-	S	-	0	!	S	S	S	4	r++
cleandesc=INC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=HL*++	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=INC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=HL*++	tstates=11 }}	INC (HL)	Indirect	-	S	-	0	!	S	S	S	11	HL*++
cleandesc=INC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=(IXY+d)*++	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=INC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=-	neffect=0	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=(IXY+d)*++	tstates=23 }}	INC (IXY+d)	Indexed	-	S	-	0	!	S	S	S	23	(IXY+d)*++
cleandesc=INC BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr++	tstates=6 }} {{#cargo_store: _table = Opcode	cleandesc=INC BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr++	tstates=6 }}	INC BC/DE/HL/SP	Register	-	S	-	-	-	-	-	-	6	rr++
cleandesc=INC IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr++	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=INC IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr++	tstates=10 }}	INC IXY	Register	-	S	-	-	-	-	-	-	10	rr++

Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.

INC A is faster than ADD 1.

DEC

{{#subobject:DEC r {{#subobject:DEC (HL) {{#subobject:DEC (IXY+d) {{#subobject:DEC BC/DE/HL/SP {{#subobject:DEC IXY

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=DEC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=r--	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=DEC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=r--	tstates=4 }}	DEC r	Register	-	S	-	1	!	S	S	S	4	r--
cleandesc=DEC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=HL*--	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=DEC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=HL*--	tstates=11 }}	DEC (HL)	Indirect	-	S	-	1	!	S	S	S	11	HL*--
cleandesc=DEC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=(IXY+D)*--	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=DEC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=(IXY+D)*--	tstates=23 }}	DEC (IXY+d)	Indexed	-	S	-	1	!	S	S	S	23	(IXY+D)*--
cleandesc=DEC BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr--	tstates=6 }} {{#cargo_store: _table = Opcode	cleandesc=DEC BC/DE/HL/SP	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr--	tstates=6 }}	DEC BC/DE/HL/SP	Register	-	S	-	-	-	-	-	-	6	rr--
cleandesc=DEC IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr--	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=DEC IXY	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=rr--	tstates=10 }}	DEC IXY	Register	-	S	-	-	-	-	-	-	10	rr--

Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.

DEC A is faster than SUB 1.

RLC (Rotate Left and Copy)

{{#subobject:RLC r {{#subobject:RLC (HL) {{#subobject:RLC (IXY+d) {{#subobject:RLC r,(IX+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RLC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[7]; r:=r<<1; r[0]:=x; CF:=x	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=RLC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[7]; r:=r<<1; r[0]:=x; CF:=x	tstates=8 }}	RLC r	Register	-	S	!	P	S	S	8	x:=r[7]; r:=r<<1; r[0]:=x; CF:=x
cleandesc=RLC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[7]; HL:=HL<<1; HL[0]:=x; CF:=x	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=RLC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[7]; HL:=HL<<1; HL[0]:=x; CF:=x	tstates=15 }}	RLC (HL)	Indirect	-	S	!	P	S	S	15	x:=HL[7]; HL:=HL<<1; HL[0]:=x; CF:=x
cleandesc=RLC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[7]; (IXY+d):=(IXY+d)<<1; (IXY+d)[0]:=x; CF:=x	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RLC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[7]; (IXY+d):=(IXY+d)<<1; (IXY+d)[0]:=x; CF:=x	tstates=23 }}	RLC (IXY+d)	Indexed	-	S	!	P	S	S	23	x:=(IXY+d)[7]; (IXY+d):=(IXY+d)<<1; (IXY+d)[0]:=x; CF:=x
cleandesc=RLC r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[7]; (IX+d):=(IX+d)<<1; (IX+d)[0]:=x; CF:=x; r:=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RLC r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[7]; (IX+d):=(IX+d)<<1; (IX+d)[0]:=x; CF:=x; r:=(IX+d)*	tstates=23 }}	RLC r,(IX+d)	Register	Indexed	U	!	P	S	S	23	x:=(IX+d)[7]; (IX+d):=(IX+d)<<1; (IX+d)[0]:=x; CF:=x; r:=(IX+d)*

Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation.

RL (Rotate Left)

{{#subobject:RL r {{#subobject:RL (HL) {{#subobject:RL (IXY+d) {{#subobject:RL r,(IX+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RL r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=RL r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x	tstates=8 }}	RL r	Register	-	S	!	P	S	S	8	x:=r[7]; r:=r<<1; r[0]:=CF; CF:=x
cleandesc=RL (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[7]; HL:=HL<<1; HL[0]:=CF; CF:=x	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=RL (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[7]; HL:=HL<<1; HL[0]:=CF; CF:=x	tstates=15 }}	RL (HL)	Indirect	-	S	!	P	S	S	15	x:=HL[7]; HL:=HL<<1; HL[0]:=CF; CF:=x
cleandesc=RL (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[7]; (IXY+d):=(IXY+d)<<1; (IXY+d)[0]:=CF; CF:=x	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RL (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[7]; (IXY+d):=(IXY+d)<<1; (IXY+d)[0]:=CF; CF:=x	tstates=23 }}	RL (IXY+d)	Indexed	-	S	!	P	S	S	23	x:=(IXY+d)[7]; (IXY+d):=(IXY+d)<<1; (IXY+d)[0]:=CF; CF:=x
cleandesc=RL r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[7]; (IX+d):=(IX+d)<<1; (IX+d)[0]:=CF; CF:=x; r:=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RL r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[7]; (IX+d):=(IX+d)<<1; (IX+d)[0]:=CF; CF:=x; r:=(IX+d)*	tstates=23 }}	RL r,(IX+d)	Register	Indexed	U	!	P	S	S	23	x:=(IX+d)[7]; (IX+d):=(IX+d)<<1; (IX+d)[0]:=CF; CF:=x; r:=(IX+d)*

Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.

RRC, RR (Rotate Right and Copy, Rotate Right)

{{#subobject:RRC r {{#subobject:RRC (HL) {{#subobject:RRC (IXY+d) {{#subobject:RRC r,(IX+d) {{#subobject:RR r {{#subobject:RR (HL) {{#subobject:RR (IXY+d) {{#subobject:RR r,(IX+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RRC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[0]; r:=r>>1; r[7]:=x; CF:=x	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=RRC r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[0]; r:=r>>1; r[7]:=x; CF:=x	tstates=8 }}	RRC r	Register	-	S	!	P	S	S	8	x:=r[0]; r:=r>>1; r[7]:=x; CF:=x
cleandesc=RRC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[0]; HL:=HL>>1; HL[7]:=x; CF:=x	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=RRC (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[0]; HL:=HL>>1; HL[7]:=x; CF:=x	tstates=15 }}	RRC (HL)	Indirect	-	S	!	P	S	S	15	x:=HL[0]; HL:=HL>>1; HL[7]:=x; CF:=x
cleandesc=RRC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[0]; (IXY+d):=(IXY+d)>>1; (IXY+d)[7]:=x; CF:=x	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RRC (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[0]; (IXY+d):=(IXY+d)>>1; (IXY+d)[7]:=x; CF:=x	tstates=23 }}	RRC (IXY+d)	Indexed	-	S	!	P	S	S	23	x:=(IXY+d)[0]; (IXY+d):=(IXY+d)>>1; (IXY+d)[7]:=x; CF:=x
cleandesc=RRC r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[0]; (IX+d):=(IX+d)>>1; (IX+d)[7]:=x; CF:=x; r:=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RRC r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[0]; (IX+d):=(IX+d)>>1; (IX+d)[7]:=x; CF:=x; r:=(IX+d)*	tstates=23 }}	RRC r,(IX+d)	Register	Indexed	U	!	P	S	S	23	x:=(IX+d)[0]; (IX+d):=(IX+d)>>1; (IX+d)[7]:=x; CF:=x; r:=(IX+d)*
cleandesc=RR r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=RR r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x	tstates=8 }}	RR r	Register	-	S	!	P	S	S	8	x:=r[0]; r:=r>>1; r[7]:=CF; CF:=x
cleandesc=RR (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[0]; HL:=HL>>1; HL[7]:=CF; CF:=x	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=RR (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=HL[0]; HL:=HL>>1; HL[7]:=CF; CF:=x	tstates=15 }}	RR (HL)	Indirect	-	S	!	P	S	S	15	x:=HL[0]; HL:=HL>>1; HL[7]:=CF; CF:=x
cleandesc=RR (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[0]; (IXY+d):=(IXY+d)>>1; (IXY+d)[7]:=CF; CF:=x	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RR (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IXY+d)[0]; (IXY+d):=(IXY+d)>>1; (IXY+d)[7]:=CF; CF:=x	tstates=23 }}	RR (IXY+d)	Indexed	-	S	!	P	S	S	23	x:=(IXY+d)[0]; (IXY+d):=(IXY+d)>>1; (IXY+d)[7]:=CF; CF:=x
cleandesc=RR r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[0]; (IX+d):=(IX+d)>>1; (IX+d)[7]:=CF; CF:=x; r=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RR r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x:=(IX+d)[0]; (IX+d):=(IX+d)>>1; (IX+d)[7]:=CF; CF:=x; r=(IX+d)*	tstates=23 }}	RR r,(IX+d)	Register	Indexed	U	!	P	S	S	23	x:=(IX+d)[0]; (IX+d):=(IX+d)>>1; (IX+d)[7]:=CF; CF:=x; r=(IX+d)*

Same as RLC and RL except they rotate right instead of left.

SLA (Shift Left Arithmetic)

{{#subobject:SLA r {{#subobject:SLA (HL) {{#subobject:SLA (IXY+d) {{#subobject:SLA r,(IX+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SLA r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r:=r<<1	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SLA r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r:=r<<1	tstates=8 }}	SLA r	Register	-	S	!	P	S	S	8	r:=r<<1
cleandesc=SLA (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=HL:=HL<<1	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=SLA (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=HL:=HL<<1	tstates=15 }}	SLA (HL)	Indirect	-	S	!	P	S	S	15	HL:=HL<<1
cleandesc=SLA (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=(IXY+d)<<1	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SLA (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=(IXY+d)<<1	tstates=23 }}	SLA (IXY+d)	Indexed	-	S	!	P	S	S	23	(IXY+d):=(IXY+d)<<1
cleandesc=SLA r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IX+d):=(IX+d)<<1; r=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SLA r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IX+d):=(IX+d)<<1; r=(IX+d)*	tstates=23 }}	SLA r,(IX+d)	Register	Indexed	U	!	P	S	S	23	(IX+d):=(IX+d)<<1; r=(IX+d)*

Same as RL except bit 0 is set to zero, not the previous contents of Carry.

SRA (Shift Right Arithmetic)

{{#subobject:SRA r {{#subobject:SRA (HL) {{#subobject:SRA (IXY+d) {{#subobject:SRA r,(IX+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SRA r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r:=r>>1 OR r[7]	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SRA r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r:=r>>1 OR r[7]	tstates=8 }}	SRA r	Register	-	S	!	P	S	S	8	r:=r>>1 OR r[7]
cleandesc=SRA (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=HL:=HL>>1 OR HL*[7]	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=SRA (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=HL:=HL>>1 OR HL*[7]	tstates=15 }}	SRA (HL)	Indirect	-	S	!	P	S	S	15	HL:=HL>>1 OR HL*[7]
cleandesc=SRA (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=(IXY+d)>>1 OR (IXY+d)*[7]	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SRA (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=(IXY+d)>>1 OR (IXY+d)*[7]	tstates=23 }}	SRA (IXY+d)	Indexed	-	S	!	P	S	S	23	(IXY+d):=(IXY+d)>>1 OR (IXY+d)*[7]
cleandesc=SRA r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IX+d):=(IX+d)>>1 OR (IX+d)[7]; r:=(IX+d)	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SRA r,(IX+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IX+d):=(IX+d)>>1 OR (IX+d)[7]; r:=(IX+d)	tstates=23 }}	SRA r,(IX+d)	Register	Indexed	U	!	P	S	S	23	(IX+d):=(IX+d)>>1 OR (IX+d)[7]; r:=(IX+d)

Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry.

SRL (Shift Right Logical)

{{#subobject:SRL r {{#subobject:SRL (HL) {{#subobject:SRL (IXY+d) {{#subobject:SRL r,(IXY+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SRL r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=r:=unsigned(r)>>1	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SRL r	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=r:=unsigned(r)>>1	tstates=8 }}	SRL r	Register	-	S	!	P	S	8	r:=unsigned(r)>>1
cleandesc=SRL (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=HL:=unsigned(HL)>>1	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=SRL (HL)	status=S	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=HL:=unsigned(HL)>>1	tstates=15 }}	SRL (HL)	Indirect	-	S	!	P	S	15	HL:=unsigned(HL)>>1
cleandesc=SRL (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=(IXY+d):=unsigned((IXY+d))>>1	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SRL (IXY+d)	status=S	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=(IXY+d):=unsigned((IXY+d))>>1	tstates=23 }}	SRL (IXY+d)	Indexed	-	S	!	P	S	23	(IXY+d):=unsigned((IXY+d))>>1
cleandesc=SRL r,(IXY+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=(IXY+d):=unsigned((IXY+d))>>1; r:=(IXY+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SRL r,(IXY+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=0	shortfx=(IXY+d):=unsigned((IXY+d))>>1; r:=(IXY+d)*	tstates=23 }}	SRL r,(IXY+d)	Register	Indexed	U	!	P	S	23	(IXY+d):=unsigned((IXY+d))>>1; r:=(IXY+d)*

Same as SLA except it shifts right instead of left.

RLCA, RLA, RRCA, RRA

{{#subobject:RLCA {{#subobject:RLA {{#subobject:RRCA {{#subobject:RRA

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RLCA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[7]; A:=A<<1; A[0]:=x; CF:=x	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=RLCA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[7]; A:=A<<1; A[0]:=x; CF:=x	tstates=4 }}	RLCA	-	-	S	!	-	-	-	4	x:=A[7]; A:=A<<1; A[0]:=x; CF:=x
cleandesc=RLA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=RLA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x	tstates=4 }}	RLA	-	-	S	!	-	-	-	4	x:=A[7]; A:=A<<1; A[0]:=CF; CF:=x
cleandesc=RRCA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[0]; A:=A>>1; A[7]:=x; CF:=x	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=RRCA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[0]; A:=A>>1; A[7]:=x; CF:=x	tstates=4 }}	RRCA	-	-	S	!	-	-	-	4	x:=A[0]; A:=A>>1; A[7]:=x; CF:=x
cleandesc=RRA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=RRA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x	tstates=4 }}	RRA	-	-	S	!	-	-	-	4	x:=A[0]; A:=A>>1; A[7]:=CF; CF:=x

Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.

SLL (Shift Left Logical): This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.

SL1 or SLI (Shift Left and Add 1) or (Shift Left and Increment)

{{#subobject:SL1 r {{#subobject:SL1 (HL) {{#subobject:SL1 (IXY+d) {{#subobject:SL1 r,(IXY+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SL1 r	status=U	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r:=(r<<1)+1	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SL1 r	status=U	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r:=(r<<1)+1	tstates=8 }}	SL1 r	Register	-	U	!	P	S	S	8	r:=(r<<1)+1
cleandesc=SL1 (HL)	status=U	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=HL:=(HL<<1)+1	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=SL1 (HL)	status=U	isZ80Instruction=y	admode1=Indirect	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=HL:=(HL<<1)+1	tstates=15 }}	SL1 (HL)	Indirect	-	U	!	P	S	S	15	HL:=(HL<<1)+1
cleandesc=SL1 (IXY+d)	status=U	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=((IXY+d)<<1)+1	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SL1 (IXY+d)	status=U	isZ80Instruction=y	admode1=Indexed	admode2=-	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=((IXY+d)<<1)+1	tstates=23 }}	SL1 (IXY+d)	Indexed	-	U	!	P	S	S	23	(IXY+d):=((IXY+d)<<1)+1
cleandesc=SL1 r,(IXY+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=((IXY+d)<<1)+1; r=(IXY+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SL1 r,(IXY+d)	status=U	isZ80Instruction=y	admode1=Register	admode2=Indexed	ceffect=!	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=(IXY+d):=((IXY+d)<<1)+1; r=(IXY+d)*	tstates=23 }}	SL1 r,(IXY+d)	Register	Indexed	U	!	P	S	S	23	(IXY+d):=((IXY+d)<<1)+1; r=(IXY+d)*

Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.

RLD

{{#subobject:RLD

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RLD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x=HL; HL[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]	tstates=18 }} {{#cargo_store: _table = Opcode	cleandesc=RLD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x=HL; HL[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]	tstates=18 }}	RLD	-	-	S	-	0	P	0	S	S	18	x=HL; HL[0123]:=A[0123]; HL*[7654]:=x[0123]; A[0123]:=x[7654]

Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.

RRD

{{#subobject:RRD

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RRD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x=HL; HL[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]	tstates=18 }} {{#cargo_store: _table = Opcode	cleandesc=RRD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=x=HL; HL[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]	tstates=18 }}	RRD	-	-	S	-	0	P	0	S	S	18	x=HL; HL[7654]:=A[0123]; HL*[0123]:=x[7654]; A[0123]:=x[0123]

Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.

Barrel (variable amount) shift and rotate (cores v2+ only)

{{#subobject:BSLA DE,B {{#subobject:BSRA DE,B {{#subobject:BSRL DE,B {{#subobject:BSRF DE,B {{#subobject:BRLC DE,B

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=BSLA DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=DE<<(B&31)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=BSLA DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=DE<<(B&31)	tstates=8 }}	BSLA DE,B	-	-	E	-	-	-	-	-	-	8	DE:=DE<<(B&31)
cleandesc=BSRA DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=signed(DE)>>(B&31)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=BSRA DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=signed(DE)>>(B&31)	tstates=8 }}	BSRA DE,B	-	-	E	-	-	-	-	-	-	8	DE:=signed(DE)>>(B&31)
cleandesc=BSRL DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=unsigned(DE)>>(B&31)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=BSRL DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=unsigned(DE)>>(B&31)	tstates=8 }}	BSRL DE,B	-	-	E	-	-	-	-	-	-	8	DE:=unsigned(DE)>>(B&31)
cleandesc=BSRF DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=~(unsigned(~DE)>>(B&31))	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=BSRF DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=~(unsigned(~DE)>>(B&31))	tstates=8 }}	BSRF DE,B	-	-	E	-	-	-	-	-	-	8	DE:=~(unsigned(~DE)>>(B&31))
cleandesc=BRLC DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=DE<<(B&15) OR DE>>(16-B&15)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=BRLC DE,B	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=DE<<(B&15) OR DE>>(16-B&15)	tstates=8 }}	BRLC DE,B	-	-	E	-	-	-	-	-	-	8	DE:=DE<<(B&15) OR DE>>(16-B&15)

Shift instructions use only bits 4..0 of B, BSLA shifts DE left, BSRA/BSRL/BSRF shifts DE right in arithmetic/logical/fill-one way. BRLC rotates DE left by B places, uses only bits 3..0 of B (to rotate right, use B=16-places).

CPL (ComPLement)

{{#subobject:CPL

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CPL	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=-	heffect=1	zeffect=-	seffect=-	shortfx=A:=~A	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=CPL	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=-	heffect=1	zeffect=-	seffect=-	shortfx=A:=~A	tstates=4 }}	CPL	-	-	S	-	1	-	1	-	-	4	A:=~A

Inverts the contents of the accumulator.

NEG (NEGate)

{{#subobject:NEG

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=NEG	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=A:=0-A	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=NEG	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=1	pveffect=!	heffect=S	zeffect=S	seffect=S	shortfx=A:=0-A	tstates=8 }}	NEG	-	-	S	!	1	!	S	S	S	8	A:=0-A

Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.

CCF (Change Carry Flag)

{{#subobject:CCF

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CCF	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=!	zeffect=-	seffect=-	shortfx=CF:=!CF	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=CCF	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=0	pveffect=-	heffect=!	zeffect=-	seffect=-	shortfx=CF:=!CF	tstates=4 }}	CCF	-	-	S	!	0	-	!	-	-	4	CF:=!CF

Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.

SCF (Set Carry Flag)

{{#subobject:SCF

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SCF	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=1	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=CF:=1	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=SCF	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=1	neffect=0	pveffect=-	heffect=0	zeffect=-	seffect=-	shortfx=CF:=1	tstates=4 }}	SCF	-	-	S	1	0	-	0	-	-	4	CF:=1

Sets the carry flag.

BIT

{{#subobject:BIT b,r {{#subobject:BIT b,(HL) {{#subobject:BIT b,(IXY+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=BIT b,r	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=0	pveffect=?	heffect=1	zeffect=!	seffect=?	shortfx=r[b]==1?	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=BIT b,r	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=0	pveffect=?	heffect=1	zeffect=!	seffect=?	shortfx=r[b]==1?	tstates=8 }}	BIT b,r	Immediate	Register	S	-	?	1	!	?	8	r[b]==1?
cleandesc=BIT b,(HL)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indirect	ceffect=-	neffect=0	pveffect=?	heffect=1	zeffect=!	seffect=?	shortfx=HL*[b]==1?	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=BIT b,(HL)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indirect	ceffect=-	neffect=0	pveffect=?	heffect=1	zeffect=!	seffect=?	shortfx=HL*[b]==1?	tstates=12 }}	BIT b,(HL)	Immediate	Indirect	S	-	?	1	!	?	12	HL*[b]==1?
cleandesc=BIT b,(IXY+d)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=0	pveffect=?	heffect=1	zeffect=!	seffect=?	shortfx=(IXY+d)*[b]==1?	tstates=20 }} {{#cargo_store: _table = Opcode	cleandesc=BIT b,(IXY+d)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=0	pveffect=?	heffect=1	zeffect=!	seffect=?	shortfx=(IXY+d)*[b]==1?	tstates=20 }}	BIT b,(IXY+d)	Immediate	Indexed	S	-	?	1	!	?	20	(IXY+d)*[b]==1?

Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.

SET

{{#subobject:SET b,r {{#subobject:SET b,(HL) {{#subobject:SET b,(IXY+d) {{#subobject:SET r,b,(IX+d) {{#subobject:SETAE

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SET b,r	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r:=r OR (1<<b)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SET b,r	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r:=r OR (1<<b)	tstates=8 }}	SET b,r	Immediate	Register	S	-	-	-	-	-	-	8	r:=r OR (1<<b)
cleandesc=SET b,(HL)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL:=HL OR (1<<b)	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=SET b,(HL)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL:=HL OR (1<<b)	tstates=15 }}	SET b,(HL)	Immediate	Register	S	-	-	-	-	-	-	15	HL:=HL OR (1<<b)
cleandesc=SET b,(IXY+d)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+d):=(IXY+d) OR (1<<b)	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SET b,(IXY+d)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+d):=(IXY+d) OR (1<<b)	tstates=23 }}	SET b,(IXY+d)	Immediate	Indexed	S	-	-	-	-	-	-	23	(IXY+d):=(IXY+d) OR (1<<b)
cleandesc=SET r,b,(IX+d)	status=U	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IX+d):=(IX+d) OR (1<<b); r:=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=SET r,b,(IX+d)	status=U	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IX+d):=(IX+d) OR (1<<b); r:=(IX+d)*	tstates=23 }}	SET r,b,(IX+d)	Immediate	Indexed	U	-	-	-	-	-	-	23	(IX+d):=(IX+d) OR (1<<b); r:=(IX+d)*
cleandesc=SETAE	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A:=unsigned($80)>>(E&7)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SETAE	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A:=unsigned($80)>>(E&7)	tstates=8 }}	SETAE	-	-	E	-	-	-	-	-	-	8	A:=unsigned($80)>>(E&7)

Sets the numbered bit on target value. The possible targets are the same as BIT. The three parameter variant is undocumented and stores the result in a register as well as performing the SET.

SETAE is a Next extended opcode which takes the bit number to set from E (only the low 3 bits) and sets whole A to value of that bit, but counted from top to bottom (E=0 will produce A:=$80, E=7 will produce A:=$01). This works as pixel mask for ULA bitmap modes, when E is 0..255 x-coordinate.

RES (RESet)

{{#subobject:RES b,r {{#subobject:RES b,(HL) {{#subobject:RES b,(IXY+d) {{#subobject:RES r,b,(IX+d)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RES b,r	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r:=r & (~(1<<b))	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=RES b,r	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=r:=r & (~(1<<b))	tstates=8 }}	RES b,r	Immediate	Register	S	-	-	-	-	-	-	8	r:=r & (~(1<<b))
cleandesc=RES b,(HL)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL:=HL & (~(1<<b))	tstates=15 }} {{#cargo_store: _table = Opcode	cleandesc=RES b,(HL)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL:=HL & (~(1<<b))	tstates=15 }}	RES b,(HL)	Immediate	Register	S	-	-	-	-	-	-	15	HL:=HL & (~(1<<b))
cleandesc=RES b,(IXY+d)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+d):=(IXY+d) & (~(1<<b))	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RES b,(IXY+d)	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IXY+d):=(IXY+d) & (~(1<<b))	tstates=23 }}	RES b,(IXY+d)	Immediate	Indexed	S	-	-	-	-	-	-	23	(IXY+d):=(IXY+d) & (~(1<<b))
cleandesc=RES r,b,(IX+d)	status=U	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IX+d):=(IX+d) & (~(1<<b)); r:=(IX+d)*	tstates=23 }} {{#cargo_store: _table = Opcode	cleandesc=RES r,b,(IX+d)	status=U	isZ80Instruction=y	admode1=Immediate	admode2=Indexed	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=(IX+d):=(IX+d) & (~(1<<b)); r:=(IX+d)*	tstates=23 }}	RES r,b,(IX+d)	Immediate	Indexed	U	-	-	-	-	-	-	23	(IX+d):=(IX+d) & (~(1<<b)); r:=(IX+d)*

Resets the numbered bit on target value. The possible targets are the same as BIT.

DAA (Decimal Adjust Accumulator)

{{#subobject:DAA

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=DAA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=-	pveffect=P	heffect=!	zeffect=S	seffect=S	shortfx=no short desc.	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=DAA	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=!	neffect=-	pveffect=P	heffect=!	zeffect=S	seffect=S	shortfx=no short desc.	tstates=8 }}	DAA	-	-	S	!	-	P	!	S	S	8	no short desc.

Modifies the contents of the accumulator based on the flags and the previous operation to correct for binary coded decimal (BCD).

MUL

{{#subobject:MUL

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=MUL	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=D*E	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=MUL	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=DE:=D*E	tstates=8 }}	MUL	-	-	E	-	-	-	-	-	-	8	DE:=D*E

Next extended opcode. Multiplies D by E, storing 16 bit result into DE. Does not alter any flags.

SWAPNIB

{{#subobject:SWAPNIB

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=SWAPNIB	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A:=A[3210]<<4 OR A[7654]>>4	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=SWAPNIB	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A:=A[3210]<<4 OR A[7654]>>4	tstates=8 }}	SWAPNIB	-	-	E	-	-	-	-	-	-	8	A:=A[3210]<<4 OR A[7654]>>4

Next extended opcode. Swaps the high and low nibbles of the accumulator.

PIXELAD

{{#subobject:PIXELAD

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=PIXELAD	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=PIXELAD	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)	tstates=8 }}	PIXELAD	-	-	E	-	-	-	-	-	-	8	HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)

Next extended opcode. Takes E and D as the X,Y coordinate of a point and calculates the address of the byte containing this pixel in the pixel area of standard ULA screen 0, storing it in HL.

PIXELDN

{{#subobject:PIXELDN

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=PIXELDN	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if(HL&$0700!=$0700) HL+=256; else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; else HL:=HL&$F81F+$0800	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=PIXELDN	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if(HL&$0700!=$0700) HL+=256; else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; else HL:=HL&$F81F+$0800	tstates=8 }}	PIXELDN	-	-	E	-	-	-	-	-	-	8	if(HL&$0700!=$0700) HL+=256; else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; else HL:=HL&$F81F+$0800

Updates the address in HL to move down by one line of pixels.

Control Flow

JP (JumP)

{{#subobject:JP nn {{#subobject:JP (HL) {{#subobject:JP (IXY) {{#subobject:JP (C)

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=JP nn	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=nn	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=JP nn	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=nn	tstates=10 }}	JP nn	Address	-	S	-	-	-	-	-	-	10	PC:=nn
cleandesc=JP (HL)	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=HL (not PC:=HL*)	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=JP (HL)	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=HL (not PC:=HL*)	tstates=4 }}	JP (HL)	Register	-	S	-	-	-	-	-	-	4	PC:=HL (not PC:=HL*)
cleandesc=JP (IXY)	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=IXY (not PC:=IXY*)	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=JP (IXY)	status=S	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=IXY (not PC:=IXY*)	tstates=8 }}	JP (IXY)	Register	-	S	-	-	-	-	-	-	8	PC:=IXY (not PC:=IXY*)
cleandesc=JP (C)	status=E	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=?	neffect=?	pveffect=?	heffect=?	zeffect=?	seffect=?	shortfx=PC:=PC&$C000+IN(C)<<6	tstates=13 }} {{#cargo_store: _table = Opcode	cleandesc=JP (C)	status=E	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=?	neffect=?	pveffect=?	heffect=?	zeffect=?	seffect=?	shortfx=PC:=PC&$C000+IN(C)<<6	tstates=13 }}	JP (C)	Register	-	E	?	?	?	?	?	?	13	PC:=PC&$C000+IN(C)<<6

Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs look like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to. The JP (C) sets bottom 14 bits of current PC^* to value read from I/O port: PC[13:0] = (IN (C) << 6) (can be used to execute code block read from a disk stream) * "current PC" is address of next instruction after JP (C), as the PC is advanced by fetching op code from memory and is already advanced when execution happens - if the JP instruction resides at the very end of 16k memory block (..FE or ..FF address), then newly composed PC value will land into following 16k block.

JP cc

{{#subobject:JP Z/NZ/NC/C/PO/PE/P/M, nn

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=JP Z/NZ/NC/C/PO/PE/P/M, nn	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc PC:=nn	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=JP Z/NZ/NC/C/PO/PE/P/M, nn	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc PC:=nn	tstates=10 }}	JP Z/NZ/NC/C/PO/PE/P/M, nn	Address	-	S	-	-	-	-	-	-	10	if cc PC:=nn

Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.

JR (Jump Relative)

{{#subobject:JR nn {{#subobject:JR C/NC/Z/NZ, nn

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=JR nn	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC+=nn	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=JR nn	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC+=nn	tstates=12 }}	JR nn	Immediate	-	S	-	-	-	-	-	-	12	PC+=nn
cleandesc=JR C/NC/Z/NZ, nn	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc PC+=nn	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=JR C/NC/Z/NZ, nn	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc PC+=nn	tstates=12 }}	JR C/NC/Z/NZ, nn	Immediate	-	S	-	-	-	-	-	-	12	if cc PC+=nn

Jumps to an alternate address by adding the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.

DJNZ (Decrement and Jump if Not Zero)

{{#subobject:DJNZ n

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=DJNZ n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=B--; if B!=0 PC+=nn	tstates=13 }} {{#cargo_store: _table = Opcode	cleandesc=DJNZ n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=B--; if B!=0 PC+=nn	tstates=13 }}	DJNZ n	Immediate	-	S	-	-	-	-	-	-	13	B--; if B!=0 PC+=nn

Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.

CALL

{{#subobject:CALL nn {{#subobject:CALL Z/NZ/C/NC/PO/PE/P/M, n

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=CALL nn	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=PC; PC:=nn	tstates=17 }} {{#cargo_store: _table = Opcode	cleandesc=CALL nn	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=SP-=2; SP*:=PC; PC:=nn	tstates=17 }}	CALL nn	Address	-	S	-	-	-	-	-	-	17	SP-=2; SP*:=PC; PC:=nn
cleandesc=CALL Z/NZ/C/NC/PO/PE/P/M, n	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc {SP-=2; SP*:=PC; PC:=nn}	tstates=17 }} {{#cargo_store: _table = Opcode	cleandesc=CALL Z/NZ/C/NC/PO/PE/P/M, n	status=S	isZ80Instruction=y	admode1=Address	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc {SP-=2; SP*:=PC; PC:=nn}	tstates=17 }}	CALL Z/NZ/C/NC/PO/PE/P/M, n	Address	-	S	-	-	-	-	-	-	17	if cc {SP-=2; SP*:=PC; PC:=nn}

Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls.

If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)

RET

{{#subobject:RET {{#subobject:RET Z/NZ/C/NC/PO/PE/P/M

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RET	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=SP*; SP+=2	tstates=10 }} {{#cargo_store: _table = Opcode	cleandesc=RET	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=SP*; SP+=2	tstates=10 }}	RET	-	-	S	-	-	-	-	-	-	10	PC:=SP*; SP+=2
cleandesc=RET Z/NZ/C/NC/PO/PE/P/M	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc {PC:=SP*; SP+=2}	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=RET Z/NZ/C/NC/PO/PE/P/M	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=if cc {PC:=SP*; SP+=2}	tstates=11 }}	RET Z/NZ/C/NC/PO/PE/P/M	-	-	S	-	-	-	-	-	-	11	if cc {PC:=SP*; SP+=2}

POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.

RETI

{{#subobject:RETI

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RETI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=SP*; SP+=2	tstates=14 }} {{#cargo_store: _table = Opcode	cleandesc=RETI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC:=SP*; SP+=2	tstates=14 }}	RETI	-	-	S	-	-	-	-	-	-	14	PC:=SP*; SP+=2

Returns from an interrupt service routine (same as RET instruction, but also does signal to I/O device that the interrupt routine is completed).

RETN

{{#subobject:RETN

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RETN	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=IFF1:=IFF2; PC:=SP*; SP+=2	tstates=14 }} {{#cargo_store: _table = Opcode	cleandesc=RETN	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=IFF1:=IFF2; PC:=SP*; SP+=2	tstates=14 }}	RETN	-	-	S	-	-	-	-	-	-	14	IFF1:=IFF2; PC:=SP*; SP+=2

Returns from a non-maskable interrupt service routine.

RST (ReSTart)

{{#subobject:RST n

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=RST n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=CALL n	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=RST n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=CALL n	tstates=11 }}	RST n	Immediate	-	S	-	-	-	-	-	-	11	CALL n

Performs a CALL to a routine located at one of eight fixed locations ($00, $08, ..., $38) in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines.

NOP (No OPeration)

{{#subobject:NOP

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=NOP	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC+=1	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=NOP	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=PC+=1	tstates=4 }}	NOP	-	-	S	-	-	-	-	-	-	4	PC+=1

Does "nothing" (just usual housekeeping like refreshing memory and advancing program counter to next instruction).

HALT

{{#subobject:HALT

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=HALT	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=waits for interrupt	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=HALT	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=waits for interrupt	tstates=4 }}	HALT	-	-	S	-	-	-	-	-	-	4	waits for interrupt

Suspends the CPU until an interrupt is received (maskable interrupts must be enabled to break the wait). While CPU is waiting for interrupt, the fake NOP instruction is being executed, to keep memory refresh going on.

DI (Disable Interrupts)

{{#subobject:DI

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=DI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=IFF1:=0; IFF2:=0	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=DI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=IFF1:=0; IFF2:=0	tstates=4 }}	DI	-	-	S	-	-	-	-	-	-	4	IFF1:=0; IFF2:=0

Disables maskable interrupts.

EI (Enable Interrupts)

{{#subobject:EI

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=EI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=IFF1:=1; IFF2:=1	tstates=4 }} {{#cargo_store: _table = Opcode	cleandesc=EI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=IFF1:=1; IFF2:=1	tstates=4 }}	EI	-	-	S	-	-	-	-	-	-	4	IFF1:=1; IFF2:=1

Enables maskable interrupts (after next instruction, i.e. for example "EI RET" - the interrupt may happen only after RET instruction is finished (or "EI DI" pair of instructions will not allow any maskable interrupt to happen).

IM (Interrupt Mode)

{{#subobject:IM n

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=IM n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=Interrupt mode:=n	tstates=8 }} {{#cargo_store: _table = Opcode	cleandesc=IM n	status=S	isZ80Instruction=y	admode1=Immediate	admode2=-	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=Interrupt mode:=n	tstates=8 }}	IM n	Immediate	-	S	-	-	-	-	-	-	8	Interrupt mode:=n

Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)

Input and Output

IN r, (c); OUT (c), r

{{#subobject:IN r, (c) {{#subobject:OUT (c),r

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=IN r, (c)	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r := in(BC)	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=IN r, (c)	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=r := in(BC)	tstates=12 }}	IN r, (c)	Register	Register	S	-	0	P	0	S	S	12	r := in(BC)
cleandesc=OUT (c),r	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out(BC,r)	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=OUT (c),r	status=S	isZ80Instruction=y	admode1=Register	admode2=Register	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out(BC,r)	tstates=12 }}	OUT (c),r	Register	Register	S	-	-	-	-	-	-	12	out(BC,r)

Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.

IN (c); OUT (c), 0

{{#subobject:IN (c) {{#subobject:OUT (c),0

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=IN (c)	status=U	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=in(BC)?	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=IN (c)	status=U	isZ80Instruction=y	admode1=Register	admode2=-	ceffect=-	neffect=0	pveffect=P	heffect=0	zeffect=S	seffect=S	shortfx=in(BC)?	tstates=12 }}	IN (c)	Register	-	U	-	0	P	0	S	S	12	in(BC)?
cleandesc=OUT (c),0	status=U	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out(BC,0)	tstates=12 }} {{#cargo_store: _table = Opcode	cleandesc=OUT (c),0	status=U	isZ80Instruction=y	admode1=Register	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out(BC,0)	tstates=12 }}	OUT (c),0	Register	Immediate	U	-	-	-	-	-	-	12	out(BC,0)

Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode.

IN a, (n); OUT (n), a

{{#subobject:IN A, (n) {{#subobject:OUT (n),A

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=IN A, (n)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A := in(An)	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=IN A, (n)	status=S	isZ80Instruction=y	admode1=Accumulator	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=A := in(An)	tstates=11 }}	IN A, (n)	Accumulator	Immediate	S	-	-	-	-	-	-	11	A := in(An)
cleandesc=OUT (n),A	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out(An,A)	tstates=11 }} {{#cargo_store: _table = Opcode	cleandesc=OUT (n),A	status=S	isZ80Instruction=y	admode1=Immediate	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out(An,A)	tstates=11 }}	OUT (n),A	Immediate	Accumulator	S	-	-	-	-	-	-	11	out(An,A)

Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.

INI (INput and Increment)

{{#subobject:INI

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=INI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=HL*:=in(BC); HL++; B--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=INI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=HL*:=in(BC); HL++; B--	tstates=16 }}	INI	-	-	S	-	1	!	!	!	!	16	HL*:=in(BC); HL++; B--

Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; S, H, and P/V are destroyed.

INIR (INput and Increment Repeated)

{{#subobject:INIR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=INIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do INI while(B>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=INIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do INI while(B>0)	tstates=21x+16 }}	INIR	-	-	S	-	1	!	!	1	!	21x+16	do INI while(B>0)

Loops INIR until B reaches 0. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant. Interrupts are recognized during execution.

IND, INDR (INput and Decrement, INput and Decrement Repeated)

{{#subobject:IND {{#subobject:INDR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=IND	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=HL*:=in(BC); HL--; B--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=IND	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=HL*:=in(BC); HL--; B--	tstates=16 }}	IND	-	-	S	-	1	!	!	!	!	16	HL*:=in(BC); HL--; B--
cleandesc=INDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do IND while(B>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=INDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do IND while(B>0)	tstates=21x+16 }}	INDR	-	-	S	-	1	!	!	1	!	21x+16	do IND while(B>0)

Behave like INI and INIR except that HL is decremented instead of incremented.

OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)

{{#subobject:OUTI {{#subobject:OTIR {{#subobject:OUTD {{#subobject:OTDR

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=OUTI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=B--; out(BC,HL*); HL++	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=OUTI	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=B--; out(BC,HL*); HL++	tstates=16 }}	OUTI	-	-	S	-	1	!	!	!	!	16	B--; out(BC,HL*); HL++
cleandesc=OTIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do OUTI while (B>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=OTIR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do OUTI while (B>0)	tstates=21x+16 }}	OTIR	-	-	S	-	1	!	!	1	!	21x+16	do OUTI while (B>0)
cleandesc=OUTD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=B--; out(BC,HL*); HL--	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=OUTD	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=!	seffect=!	shortfx=B--; out(BC,HL*); HL--	tstates=16 }}	OUTD	-	-	S	-	1	!	!	!	!	16	B--; out(BC,HL*); HL--
cleandesc=OTDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do OUTD while (B>0)	tstates=21x+16 }} {{#cargo_store: _table = Opcode	cleandesc=OTDR	status=S	isZ80Instruction=y	admode1=-	admode2=-	ceffect=-	neffect=1	pveffect=!	heffect=!	zeffect=1	seffect=!	shortfx=do OUTD while (B>0)	tstates=21x+16 }}	OTDR	-	-	S	-	1	!	!	1	!	21x+16	do OUTD while (B>0)

Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented before the output instead of after.

OUTINB (Out and Increment with No B)

{{#subobject:OUTINB

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=OUTINB	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=?	neffect=?	pveffect=?	heffect=?	zeffect=?	seffect=?	shortfx=out(BC,HL*); HL++	tstates=16 }} {{#cargo_store: _table = Opcode	cleandesc=OUTINB	status=E	isZ80Instruction=y	admode1=-	admode2=-	ceffect=?	neffect=?	pveffect=?	heffect=?	zeffect=?	seffect=?	shortfx=out(BC,HL*); HL++	tstates=16 }}	OUTINB	-	-	E	?	?	?	?	?	?	16	out(BC,HL*); HL++

Next extended opcode. Behaves like OUTI, but doesn't decrement B.

NEXTREG

{{#subobject:NEXTREG nn, nn {{#subobject:NEXTREG nn, A

Mnemonic	Addressing mode 1	Addressing mode 2	Status	C	N	PV	H	Z	S	Tstates	shortfx
cleandesc=NEXTREG nn, nn	status=E	isZ80Instruction=y	admode1=Immediate	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out($243B,nn1); out($253B,nn2)	tstates=20 }} {{#cargo_store: _table = Opcode	cleandesc=NEXTREG nn, nn	status=E	isZ80Instruction=y	admode1=Immediate	admode2=Immediate	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out($243B,nn1); out($253B,nn2)	tstates=20 }}	NEXTREG nn, nn	Immediate	Immediate	E	-	-	-	-	-	-	20	out($243B,nn1); out($253B,nn2)
cleandesc=NEXTREG nn, A	status=E	isZ80Instruction=y	admode1=Immediate	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out($243B,nn); out($253B,a)	tstates=17 }} {{#cargo_store: _table = Opcode	cleandesc=NEXTREG nn, A	status=E	isZ80Instruction=y	admode1=Immediate	admode2=Accumulator	ceffect=-	neffect=-	pveffect=-	heffect=-	zeffect=-	seffect=-	shortfx=out($243B,nn); out($253B,a)	tstates=17 }}	NEXTREG nn, A	Immediate	Accumulator	E	-	-	-	-	-	-	17	out($243B,nn); out($253B,a)

Next extended opcode. Directly sets the Next Feature Control Registers without going through ports {{#ask:

PortNumber::$243B }} ($243B{{#ask: PortNumber::$243B |mainlabel=- |headers=hide |intro= / |?NumberDec#- }}) and {{#ask: PortNumber::$253B }} ($253B{{#ask: PortNumber::$253B |mainlabel=- |headers=hide |intro= / |?NumberDec#- }}).

Z80N instructions opcodes

The Z80 on the Next has extra instructions that are unique to it. Below is a table of the opcode bytes that are required to select those instructions. The timings are based on some partial testing. These may not be accurate.

Instruction	Byte 1	Byte 2	Byte 3	Byte 4	T-States
LDIX	ED	A4			16
LDWS	ED	A5			14
LDIRX	ED	B4			21/16
LDDX	ED	AC			16
LDDRX	ED	BC			21/16
LDPIRX	ED	B7			21/16
OUTINB	ED	90			16
MUL D,E	ED	30			8
ADD HL,A	ED	31			8
ADD DE,A	ED	32			8
ADD BC,A	ED	33			8
ADD HL,$nnnn	ED	34	low	high	16
ADD DE,$nnnn	ED	35	low	high	16
ADD BC,$nnnn	ED	36	low	high	16
SWAPNIB	ED	23			8
MIRROR	ED	24			8
PUSH $nnnn	ED	8A	high	low	23
NEXTREG $rr,$nn	ED	91	register	value	20
NEXTREG $rr,A	ED	92	register		17
PIXELDN	ED	93			8
PIXELAD	ED	94			8
SETAE	ED	95			8
TEST $nn	ED	27	value		11

Also note that the "PUSH $nnnn" instruction is not a mistake. The operand is in big-endian.

The core version 2.00.22+ has these new instructions:

Instruction	Byte 1	Byte 2	T-States
BSLA DE,B	ED	28	8
BSRA DE,B	ED	29	8
BSRL DE,B	ED	2A	8
BSRF DE,B	ED	2B	8
BRLC DE,B	ED	2C	8
JP (C)	ED	98	13

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	This is a general list of Z80 instructions with descriptions. For summaries, you can view the [[Z80 Instruction Table]]. You can also [[Special:RunQuery/OpcodeQuery\|search for opcodes]].		This is a general list of Z80 instructions with descriptions. For summaries, you can view the [[Z80 Instruction Table]]. You can also [[Special:RunQuery/OpcodeQuery\|search for opcodes]].