Circuit Diagrams: Difference between revisions
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|valign=top width=50%| [[Image:DaughterLocation.jpg | |valign=top width=50%| [[Image:DaughterLocation.jpg]] | ||
|valign=top| [[Image:Circuit_daughter_board.png | |valign=top| [[Image:Circuit_daughter_board.png]] | ||
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Revision as of 19:00, 14 April 2019
J13 - Daughter board connector
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J15 - Next GPIO
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CN5 - Expansion bus (edge connector)
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J10/J11 - Memory Expansion Ports
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