Circuit Diagrams: Difference between revisions
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== Expansion bus (edge connector) == | == CN5 Expansion bus (edge connector) == | ||
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== Memory Expansion Ports == | == CN6, CN8 Memory Expansion Ports == | ||
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Revision as of 13:36, 14 April 2019
J13 - Daughter board connector
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J15 - Next GPIO
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CN5 Expansion bus (edge connector)
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CN6, CN8 Memory Expansion Ports
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