Difference between revisions of "Layer 2"
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When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled. | When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled. | ||
| − | If you need to ''read'' from Layer 2 you will need to use the regular [[Memory map | + | If you need to ''read'' from Layer 2 you will need to use the regular [[Memory map|banking]] ports to switch in one of the layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into Slot 1 is provided for convenience and to allow graphics data to also be stored in the extended banks. |
Pixels are drawn to layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate. | Pixels are drawn to layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate. | ||
Revision as of 00:40, 30 August 2017
Layer 2 is an additional graphics feature on the Next. It provides a 256-color screen at the full 256x192 resolution, in which every pixel is individually colored. Layer 2 may appear in place of, behind, or above the ULA-generated screen.
Documentation on Layer 2 is extremely sparse at the moment and could be subject to change. Information below has been taken from emulator documentation.
The layer 2 screen occupies 48k, which is stored in 3 consecutive banks. By default, banks 8-10 are used for the main layer 2 screen and banks 11-13 for the shadow layer 2 screen. These can be changed using Layer 2 RAM Page Register ($12) and Layer 2 RAM Shadow Page Register ($13).
Each pixel of layer 2 is assigned 1 byte of video memory. This means layer 2 consumes a total of 48k. Since the Spectrum banks are 16k, Layer 2 is divided vertically into 3 banks of 64 lines each, each of which is exactly 16k.
Layer 2 is controlled via Layer 2 Access Port ($123B / 4667), which is bit mapped as follows:
| Bit | Description |
|---|---|
| 6-7 | Video RAM bank select |
| 3 | Shadow Layer 2 RAM select |
| 1 | Layer 2 visible |
| 0 | Enable Layer 2 write paging |
When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by writes into slot 1, ie memory area $0000-$3fff (see Memory map). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you cannot READ the contents of layer 2 via this mapping! Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.
If you need to read from Layer 2 you will need to use the regular banking ports to switch in one of the layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into Slot 1 is provided for convenience and to allow graphics data to also be stored in the extended banks.
Pixels are drawn to layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.
Note that you will need to manually clear the layer 2 screen before drawing on it, as it may contain random data when the machine starts up.
System registers Layer 2 X Offset Register ($16) and Layer 2 Y Offset Register ($17) apply a pixel shift to all content in layer 2, allowing scrolling effects to be created.