Difference between revisions of "Video Line Interrupt Control Register"
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m (Ped7g moved page Raster Interrupt Control Register to Video Line Interrupt Control Register: sync with "nextreg.txt" terminology) |
(core 3.1.5 changes/refresh) |
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The LSB part of desired interrupt line is in {{NextRegNo|$23}}. | The LSB part of desired interrupt line is in {{NextRegNo|$23}}. | ||
| + | |||
| + | Since core 3.1.5 the numbering of lines can be offset by {{NextRegNo|$64}}. | ||
Revision as of 08:22, 27 April 2020
| Number | $22 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Controls the timing of raster interrupts and the ULA frame interrupt. |
| Bit | Function |
|---|---|
| 7 | (R) INT signal (even when Z80N has interrupts disabled) (1 = interrupt is requested)
(W) Reserved, must be 0 |
| 6-3 | Reserved, must be 0 |
| 2 | If 1 disables original ULA interrupt (Reset to 0 after a reset) |
| 1 | If 1 enables Line Interrupt (Reset to 0 after a reset) |
| 0 | MSB of Line Interrupt line value (Reset to 0 after a reset) |
The line interrupt value uses coordinate system of Copper coprocessor, i.e. line 0 is the first line of pixels. But the line-interrupt happens already when the previous line's pixel area is finished (i.e. the raster-line counter still reads "previous line" and not the one programmed for interrupt). The INT signal is raised while display beam horizontal position is between 256-319 standard pixels, precise timing of interrupt handler execution then depends on how-quickly/if the Z80 will process the INT signal.
The LSB part of desired interrupt line is in Video Line Interrupt Value Register ($23).
Since core 3.1.5 the numbering of lines can be offset by Vertical Video Line Offset Register ($64).