Difference between revisions of "Expansion Bus Enable Register"

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m (core 3.0.5 changes/refresh)
(core 3.0.5 changes/refresh)
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|Readable=Yes
 
|Readable=Yes
 
|Writable=Yes
 
|Writable=Yes
|ShortDesc=Expansion bus controls/config
+
|ShortDesc=Expansion bus enable/config
 
}}
 
}}
Read (may change in the future):
 
 
{|class="wikitable"
 
{|class="wikitable"
 
! Bit !! Description
 
! Bit !! Description
 
|-
 
|-
| 7 || ROMCS is being asserted on the expansion bus
+
| || Values affecting machine immediately
 
|-
 
|-
| 6 || Expansion bus is currently enabled
+
| 7 || 1 to enable Expansion Bus
 
|-
 
|-
| 5 || Max clock is always propagated to the expansion bus
+
| 5 || 1 to disable I/O cycles and ignore IORQULA
 
|-
 
|-
| 4 || 0 indicates the 48K rom is locked in place
+
| 4 || 1 to disable memory cycles and ignore ROMCS
 
|-
 
|-
| 3-2 || Reserved
+
| || After soft reset (will be copied to bits 7-4)
 
|-
 
|-
| 1-0 || Max cpu speed while the expansion bus is enabled
+
| 3 || 1 to enable Expansion Bus
|}
 
 
 
Write (may change in the future):
 
{|class="wikitable"
 
! Bit !! Description
 
|-
 
| 7 || Make change immediate otherwise changes are noted for next soft reset
 
|-
 
| 6 || Enable the expansion bus (hard reset = 0)
 
 
|-
 
|-
| 5 || Always propagate the max clock to the expansion bus (hard reset = 0)
+
| 1 || 1 to disable I/O cycles and ignore IORQULA
 
|-
 
|-
| 4 || 0 to lock the 48k rom in place (hard reset = 0)
+
| 0 || 1 to disable memory cycles and ignore ROMCS
|-
 
| 3-2 || Reserved, must be 0
 
|-
 
| 1-0 || CPU speed when the expansion bus is enabled (currently fixed at 00 = 3.5 MHz) (hard reset = 00)
 
 
|}
 
|}
 +
 +
Set to 0 upon hard reset.
 +
 +
(new register since core 3.0.5)
  
 
(note: Next registers with number higher than $7F are inaccessible from Copper code)
 
(note: Next registers with number higher than $7F are inaccessible from Copper code)

Revision as of 22:58, 4 December 2019

Number $80
Readable Yes
Writable Yes
Short Description Expansion bus enable/config
Bit Description
Values affecting machine immediately
7 1 to enable Expansion Bus
5 1 to disable I/O cycles and ignore IORQULA
4 1 to disable memory cycles and ignore ROMCS
After soft reset (will be copied to bits 7-4)
3 1 to enable Expansion Bus
1 1 to disable I/O cycles and ignore IORQULA
0 1 to disable memory cycles and ignore ROMCS

Set to 0 upon hard reset.

(new register since core 3.0.5)

(note: Next registers with number higher than $7F are inaccessible from Copper code)