Difference between revisions of "Next Reset Register"
From SpecNext official Wiki
(core 3.0 changes) |
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Write: | Write: | ||
bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0) | bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0) | ||
| − | bits 6: | + | bits 6:4 = Reserved, must be 0 |
| + | bit 3 = Trigger NMI debugger on NextZXOS | ||
| + | bit 2 = Must be 0 | ||
bit 1 = Generate a hard reset (reboot) | bit 1 = Generate a hard reset (reboot) | ||
bit 0 = Generate a soft reset | bit 0 = Generate a soft reset | ||
* Hard reset has precedence | * Hard reset has precedence | ||
Revision as of 23:13, 17 March 2023
| Number | $02 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Identifies type of last reset. Can be written to force reset. |
Read:
bit 7 = Indicates the reset signal to the expansion bus and esp is asserted bits 6:2 = Reserved bit 1 = Indicates the last reset was a hard reset bit 0 = Indicates the last reset was a soft reset * Only one of bits 1:0 will be set
Write:
bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0) bits 6:4 = Reserved, must be 0 bit 3 = Trigger NMI debugger on NextZXOS bit 2 = Must be 0 bit 1 = Generate a hard reset (reboot) bit 0 = Generate a soft reset * Hard reset has precedence