Difference between revisions of "Peripheral 3 Register"
From SpecNext official Wiki
(core 3.0 changes) |
(core 3.0 changes/refresh) |
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(R/W) 0x08 (08) => Peripheral 3 setting: | (R/W) 0x08 (08) => Peripheral 3 setting: | ||
| − | bit 7 = | + | bit 7 = Unlock(1)/lock(0) port $7FFD bit 5 (read 1 indicates port $7FFD is not locked) |
| − | + | bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0) | |
| − | + | bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0) | |
| − | + | bit 4 = Enable internal speaker (hard reset = 1) | |
| − | bit 6 = | + | bit 3 = Enable 8-bit DACs (A,B,C,D) (hard reset = 0) |
| − | bit 5 = | + | bit 2 = Enable port $FF Timex video mode *read* (disables floating bus on 0xff) (hard reset = 0) |
| − | bit 4 = Enable internal speaker ( | + | bit 1 = Enable Turbosound (currently selected AY is frozen when disabled) (hard reset = 0) |
| − | bit 3 = Enable | + | bit 0 = Implement Issue 2 keyboard (port $FE reads as early ZX boards) (hard reset = 0) |
| − | bit 2 = | ||
| − | bit 1 = Enable | ||
| − | bit 0 = | ||
| − | |||
| − | |||
The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF. | The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF. | ||
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bit 4 default 0 | bit 4 default 0 | ||
| − | + | - needs clarification from core team, two documents about core3.0 registers I have available contradict each other, but I guess the "0" is the correct default and the "1" in table above is obsolete setting. | |
Revision as of 12:28, 11 November 2019
| Number | $08 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | ABC/ACB Stereo, Internal Speaker, SpecDrum, Timex Video Modes, Turbo Sound Next, RAM contention and [un]lock 128k paging. |
(R/W) 0x08 (08) => Peripheral 3 setting:
bit 7 = Unlock(1)/lock(0) port $7FFD bit 5 (read 1 indicates port $7FFD is not locked) bit 6 = 1 to disable RAM and I/O port contention (soft reset = 0) bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0) bit 4 = Enable internal speaker (hard reset = 1) bit 3 = Enable 8-bit DACs (A,B,C,D) (hard reset = 0) bit 2 = Enable port $FF Timex video mode *read* (disables floating bus on 0xff) (hard reset = 0) bit 1 = Enable Turbosound (currently selected AY is frozen when disabled) (hard reset = 0) bit 0 = Implement Issue 2 keyboard (port $FE reads as early ZX boards) (hard reset = 0)
The Timex modes are operational even when bit 2 is set to zero, you can still write to port $FF with desired mode changes. Bit 2 does only enable readability of port $FF.
NEW in core 3.0:
bit 4 default 0
- needs clarification from core team, two documents about core3.0 registers I have available contradict each other, but I guess the "0" is the correct default and the "1" in table above is obsolete setting.