Difference between revisions of "Z80Next Only Instruction Table"

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In this table only the Z80Next CPU instructions are listed. This is an extract from the table of all instructions: [[Z80_Instruction_Table_NoSemantic]].
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[[isZ80Instruction::y]]
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|?cleandesc=Mnemonic
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{| class="wikitable sortable" style="margin:auto"
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|?Status=E
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|+ Next-only (Z80N) Instructions
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|?admode1=Addressing Mode 1
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|-
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|?admode2=Addressing Mode 2
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! Mnemonic !! Status !! Addressing Mode 1 !! Addressing Mode 2 || Flags: C N PV H Z S || T-States || Summary
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|?ceffect=C
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|-
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|?neffect=N
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| ADD HL/DE/BC, A || E || Register || Register || ? - - - - - || 8 || rr+=unsigned A
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|?pveffect=PV
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|-
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|?heffect=H
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| ADD HL/DE/BC, nn || E || Register || Immediate || - - - - - - || 16 || rr+=nn
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|?zeffect=Z
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|-
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|?seffect=S
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| BRLC DE,B || E || - || - || - - - - - - || 8 || DE:=DE<<(B&15) OR DE>>(16-B&15)
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  |?tstates=T-States
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|-
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|?shortfx=Summary
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| BSLA DE,B || E || - || - || - - - - - - || 8 || DE:=DE<<(B&31)
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|mainlabel=-
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|-
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}}
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| BSRA DE,B || E || - || - || - - - - - - || 8 || DE:=signed(DE)>>(B&31)
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|-
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| BSRF DE,B || E || - || - || - - - - - - || 8 || DE:=~(unsigned(~DE)>>(B&31))
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|-
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| BSRL DE,B || E || - || - || - - - - - - || 8 || DE:=unsigned(DE)>>(B&31)
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|-
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| JP (C) || E || Register || - || ? ? ? ? ? ? || 13 || PC:=PC&$C000+IN(C)<<6
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|-
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| LDDRX || E || - || - || - - - - - - || 21/16 || do LDDX while(BC>0)
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|-
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| LDDX || E || - || - || - - - - - - || 16 || {if HL*!=A DE*:=HL*;} DE++; HL--; BC--
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|-
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| LDIRX || E || - || - || - - - - - - || 21/16 || do LDIX while(BC>0)
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|-
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| LDIX || E || - || - || - - - - - - || 16 || {if HL*!=A DE*:=HL*;} DE++; HL++; BC--
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|-
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| LDPIRX || E || - || - || - - - - - - || 21/16 || do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
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|-
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| LDWS || E || - || - || - 0 ! S S S || 14 || DE*:=HL*; INC L; INC D;
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|-
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| MIRROR A || E || Register || - || - - - - - - || 8 || A[76543210]:=A[01234567]
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|-
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| MUL d,e || E || - || - || - - - - - - || 8 || DE:=D*E
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|-
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| NEXTREG n, A || E || Immediate || Accumulator || - - - - - - || 17 || HwNextReg_n:=A
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|-
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| NEXTREG n,n' || E || Immediate || Immediate || - - - - - - || 20 || HwNextReg_n:=n'
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|-
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| OUTINB || E || - || - || ? ? ? ? ? ? || 16 || out(BC,HL*); HL++
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|-
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| PIXELAD || E || - || - || - - - - - - || 8 || HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
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|-
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| PIXELDN || E || - || - || - - - - - - || 8 || if(HL&$0700!=$0700) HL+=256; else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; else HL:=HL&$F81F+$0800
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|-
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| PUSH nn || E || Immediate || - || - - - - - - || 23 || SP-=2; SP*:=nn
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|-
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| SETAE || E || - || - || - - - - - - || 8 || A:=unsigned($80)>>(E&7)
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|-
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| SWAPNIB || E || - || - || - - - - - - || 8 || A:=A[3210]<<4 OR A[7654]>>4
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|-
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| TEST n || E || Immediate || - || S ? P S S S || 11 || A&n?
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|-
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|}

Latest revision as of 16:50, 20 January 2025

In this table only the Z80Next CPU instructions are listed. This is an extract from the table of all instructions: Z80_Instruction_Table_NoSemantic.

Next-only (Z80N) Instructions
Mnemonic Status Addressing Mode 1 Addressing Mode 2 Flags: C N PV H Z S T-States Summary
ADD HL/DE/BC, A E Register Register ? - - - - - 8 rr+=unsigned A
ADD HL/DE/BC, nn E Register Immediate - - - - - - 16 rr+=nn
BRLC DE,B E - - - - - - - - 8 DE:=DE<<(B&15) OR DE>>(16-B&15)
BSLA DE,B E - - - - - - - - 8 DE:=DE<<(B&31)
BSRA DE,B E - - - - - - - - 8 DE:=signed(DE)>>(B&31)
BSRF DE,B E - - - - - - - - 8 DE:=~(unsigned(~DE)>>(B&31))
BSRL DE,B E - - - - - - - - 8 DE:=unsigned(DE)>>(B&31)
JP (C) E Register - ? ? ? ? ? ? 13 PC:=PC&$C000+IN(C)<<6
LDDRX E - - - - - - - - 21/16 do LDDX while(BC>0)
LDDX E - - - - - - - - 16 {if HL*!=A DE*:=HL*;} DE++; HL--; BC--
LDIRX E - - - - - - - - 21/16 do LDIX while(BC>0)
LDIX E - - - - - - - - 16 {if HL*!=A DE*:=HL*;} DE++; HL++; BC--
LDPIRX E - - - - - - - - 21/16 do{t:=(HL&$FFF8+E&7)*; {if t!=A DE*:=t;} DE++; BC--}while(BC>0)
LDWS E - - - 0 ! S S S 14 DE*:=HL*; INC L; INC D;
MIRROR A E Register - - - - - - - 8 A[76543210]:=A[01234567]
MUL d,e E - - - - - - - - 8 DE:=D*E
NEXTREG n, A E Immediate Accumulator - - - - - - 17 HwNextReg_n:=A
NEXTREG n,n' E Immediate Immediate - - - - - - 20 HwNextReg_n:=n'
OUTINB E - - ? ? ? ? ? ? 16 out(BC,HL*); HL++
PIXELAD E - - - - - - - - 8 HL:=$4000+((D&$C0)<<5)+((D&$07)<<8)+((D&$38)<<2)+(E>>3)
PIXELDN E - - - - - - - - 8 if(HL&$0700!=$0700) HL+=256; else if(HL&$e0!=$e0) HL:=HL&$F8FF+$20; else HL:=HL&$F81F+$0800
PUSH nn E Immediate - - - - - - - 23 SP-=2; SP*:=nn
SETAE E - - - - - - - - 8 A:=unsigned($80)>>(E&7)
SWAPNIB E - - - - - - - - 8 A:=A[3210]<<4 OR A[7654]>>4
TEST n E Immediate - S ? P S S S 11 A&n?
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