Alternate ROM

Number	$8C
Readable	Yes
Writable	Yes
Short Description	Enable alternate ROM or lock 48k ROM

Bit	Description
	Values affecting machine immediately
7	1 to enable alternate ROM
6	1 to make alternate ROM visible only during writes, 0 to make alternate ROM visible during reads
5	1 to lock ROM1 (48K ROM)
4	1 to lock ROM0 (128k ROM)
	After soft reset (will be copied to bits 7-4)
3	1 to enable alternate ROM
2	1 to make alternate ROM visible only during writes, 0 to make alternate ROM visible during reads
1	1 to lock ROM1 (48K ROM)
0	1 to lock ROM0 (128k ROM)

Set to 0 upon hard reset.

The locking mechanism also applies if the alt rom is not enabled. For the +3 and zx next, if the two lock bits are not zero, then the corresponding rom page is locked in place. Other models use the bits to preferentially lock the corresponding 48K rom or the 128K rom.

Detailed explanation from Allen based on the VHDL implementation:

The altrom behaviour is slightly different depending on the machine type (48k, 128k, +3) which is connected to the personalities. The Next is a +3 type. If the Next hardware is chosen to be a 48K machine then the Next hardware becomes 48k type and the altrom is a little different. It has to be because a 48k type machine only gets a 48k rom loaded compared to the +3 which has 64k of rom loaded.

The hardware makes a decision about which rom will be seen in the bottom 16k and it makes a decision for both cases (altrom on or altrom off) because the altrom's enable status can't be known until a memory read or write is seen.

For a +3 type machine, ie the Next, if both lock rom bits are zero (bits 5:4 of nr 0x8c), then the rom selection is determined by ports 0x7ffd and 0x1ffd like normal:

sram_active_rom <= bit 2 of port 1ffd & bit 4 of port 7ffd This is the two-bit rom number 0-3 selected if the altrom is disabled

sram_alt_128 <= not bit 4 of port 7ffd If 1, this selects the 128k altrom else the 48k altrom when altrom is enabled.

If either of the lock rom bits are non-zero (bits 5:4 of nr 0x8c) then the rom locking feature takes effect. The rom selected by ports 7ffd and 1ffd is ignored.

sram_active_rom <= nr_8c_altrom_lock_rom1 & nr_8c_altrom_lock_rom0; This is the two-bit rom number 1-3 selected if the altrom is disabled. Note you can't lock rom 0.

sram_alt_128 <= not nr_8c_altrom_lock_rom1; If 1 this selects the 128k altorm else the 48k altrom when altrom is enabled.

The decision about whether the altrom is paged into the bottom 16k (sram_alt_128) or if it's the regular rom paged in (sram_active_rom) is made when the cpu read/write signal is seen:

altrom is disabled if:

- bit 7 of nr 0x8c is 0

OR

- it's a memory read and bit 6 of nr 0x8c is 1

OR

- it's a memory write and bit 6 of nr 0x8c is 0

(new register since core 3.0.5, further slightly modified in 3.1.x cores)

(note: Next registers with number higher than $7F are inaccessible from Copper code)