Xilinx-Artix-7 FPGA: Difference between revisions

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{| class="wikitable"
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! Feature !! Spartan-6 XC6SLX16 (KS1 - Issue 2B) !! Artix-7 XC7A15T (KS2 - Issue 4) !! Artix-7 XC7A35T-2
! Feature !! Spartan-6 XC6SLX16 (KS1 - Issue 2B) !! Artix-7 XC7A15T (KS2 - Issue 4) !! Artix-7 XC7A35T-2 (KS3)
|-
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| Technology Node || 45 nm || 28 nm || 28nm
| Technology Node || 45 nm || 28 nm || 28nm

Revision as of 08:42, 19 July 2025

FPGA Upgrade: Artix-7 vs Spartan-6

The ZX Spectrum Next Kickstarter model KS2 (Issue 4 board) uses the Xilinx Artix-7 XC7A15T FPGA, replacing the Xilinx Spartan-6 XC6SLX16 FPGA used in the original KS1 (Issue 2B board). The Artix-7 is a more modern device, offering better performance, lower power consumption, and access to newer development tools.

The KS3 will use an Artix-7 XC7A35T-2 which pretty much doubles the logic cells, block RAM and DSP slices.

Below is a comparison between the two FPGAs:

Feature Spartan-6 XC6SLX16 (KS1 - Issue 2B) Artix-7 XC7A15T (KS2 - Issue 4) Artix-7 XC7A35T-2 (KS3)
Technology Node 45 nm 28 nm 28nm
Logic Cells ~14,579 ~16,640 ~33,280
Flip-Flops 18,224 20,800 41,600
Block RAM 576 Kbits 918 Kbits 1,800
DSP Slices 32 45 90
Power Consumption Higher Lower (static & dynamic) Lower (static & dynamic)
Clock Management PLL-based MMCMs and PLLs (more flexible) MMCMs and PLLs (more flexible)
Toolchain Xilinx ISE (legacy) Xilinx Vivado (modern) Xilinx Vivado (modern)
Partial Reconfiguration Not supported Supported Supported

Although the two models require different bitstreams due to the differing FPGA architectures, both systems are designed to remain feature-identical wherever possible to avoid splitting the user base.

The only additions exclusive to KS2 (Issue 4) are four extra Category:Next Configuration Registers used for low-level hardware access:

  • {{#ask:

TBRegisterNumber::$F0 }} ($F0) – XDEV CMD

  • {{#ask:

TBRegisterNumber::$F8 }} ($F8) – XADC REG

  • {{#ask:

TBRegisterNumber::$F9 }} ($F9) – XADC D0

  • {{#ask:

TBRegisterNumber::$FA }} ($FA) – XADC D1

These registers allow developers to interact with internal Xilinx features such as the DNA ID and XADC (analog-to-digital converter). Technical documentation for these registers can be found on their respective pages.

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