Tilemap Base Address Register: Difference between revisions
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:bits 5-0 = MSB of address of the tilemap in Bank 5 | :bits 5-0 = MSB of address of the tilemap in Bank 5 | ||
The value written is an offset into Bank 5 allowing the tilemap to be placed at any multiple of 256 bytes. | The value written is an offset into Bank 5 allowing the [[Tilemap|tilemap]] to be placed at any multiple of 256 bytes. | ||
Writing a physical MSB address as $40-$7F or $C0-$FF range is permitted (the top bits will be ignored). | Writing a physical MSB address as $40-$7F or $C0-$FF range is permitted (the top bits will be ignored). | ||
The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $45 the read of this register will produce value $05 (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended). | The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $45 the read of this register will produce value $05 (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended). | ||
Revision as of 05:49, 23 May 2019
| Number | TBRegisterNumber::$6E |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Base address of the 40x32 or 80x32 tile map (similar to text-mode of other computers). |
- bits 7-6 = Read back as zero, write values ignored
- bits 5-0 = MSB of address of the tilemap in Bank 5
The value written is an offset into Bank 5 allowing the tilemap to be placed at any multiple of 256 bytes.
Writing a physical MSB address as $40-$7F or $C0-$FF range is permitted (the top bits will be ignored).
The value read back may be treated as a full 8-bit value (with the top two bits equal to zero), i.e. upon writing value $45 the read of this register will produce value $05 (contrary to "reserved" bits in other registers, where read-value should be not assumed by code using it and masking by AND is recommended).