Difference between revisions of "CPU Speed Register"

Latest revision as of 19:46, 20 September 2020

Number	$07
Readable	Yes
Writable	Yes
Short Description	Sets CPU Speed, reads actual speed.

Read:

Bit	Function
7-6	Reserved
5-4	Current actual CPU speed
3-2	Reserved
1-0	Programmed CPU speed

Write:

Bit	Function
7-2	Reserved, must be 0
1-0	Set CPU speed (is set to %00 on soft reset) %00 = 3.5MHz %01 = 7MHz %10 = 14MHz %11 = 28MHz (works since core 3.0)

The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.

The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch and memory read (i.e. instruction like NOP will take 5T instead of regular 4T and DMA transfer configured to 2T+2T will take 3T+2T instead), there is some chance this may be improved in the future.

@@ Line 3: / Line 3: @@
 |Readable=Yes
 |Writable=Yes
-|ShortDesc=Sets accelerated clock speed, reads actual speed.
+|ShortDesc=Sets [[CPU Speed control|CPU Speed]], reads actual speed.
 }}
+Read:
+{| class="wikitable"
+! Bit !! Function
+|-
+| 7-6 || Reserved
+|-
+| 5-4 || Current actual CPU speed
+|-
+| 3-2 || Reserved
+|-
+| 1-0 || Programmed CPU speed
+|}
+Write:
+{| class="wikitable"
+! Bit !! Function
+|-
+| 7-2 || Reserved, must be 0
+|-
+| 1-0 || Set CPU speed (is set to %00 on soft reset)
+ %00 = 3.5MHz
+ %01 = 7MHz
+ %10 = 14MHz
+ %11 = 28MHz (works since core 3.0)
+|}
-Bit 1-0 = turbo: %00 = 3.5MHz, %01 = 7MHz, %10 = 14MHz (%00 after PoR or Hard-reset).
+The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.
-When 14MHz turbo is used, and [[Layer 2]] is enabled (bit 1 {{PortNo|$123B}}), the 14MHz speed is used only when BORDER/VBLANK/HBLANK areas of screen image are generated, during PAPER (centre 256x192 pixel area of screen) the CPU speed is dropped down to 7MHz. With [[Layer 2]] disabled, 14MHz CPU speed is stable.
+The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch and memory read (i.e. instruction like NOP will take 5T instead of regular 4T and DMA transfer configured to 2T+2T will take 3T+2T instead), there is some chance this may be improved in the future.
-Reads actual CPU speed.