Difference between revisions of "CPU Speed Register"
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m (Ped7g moved page Turbo Control Register to CPU Speed Register: syncing naming with latest nextreg.txt) |
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|Readable=Yes | |Readable=Yes | ||
|Writable=Yes | |Writable=Yes | ||
| − | |ShortDesc=Sets | + | |ShortDesc=Sets [[CPU Speed control|CPU Speed]], reads actual speed. |
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The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too. | The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too. | ||
| − | The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch (i.e. instruction like NOP will take 5T instead of regular 4T), there is some chance this may be improved in the future. | + | The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch and memory read (i.e. instruction like NOP will take 5T instead of regular 4T and DMA transfer configured to 2T+2T will take 3T+2T instead), there is some chance this may be improved in the future. |
Latest revision as of 19:46, 20 September 2020
| Number | $07 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Sets CPU Speed, reads actual speed. |
Read:
| Bit | Function |
|---|---|
| 7-6 | Reserved |
| 5-4 | Current actual CPU speed |
| 3-2 | Reserved |
| 1-0 | Programmed CPU speed |
Write:
| Bit | Function |
|---|---|
| 7-2 | Reserved, must be 0 |
| 1-0 | Set CPU speed (is set to %00 on soft reset)
%00 = 3.5MHz %01 = 7MHz %10 = 14MHz %11 = 28MHz (works since core 3.0) |
The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.
The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch and memory read (i.e. instruction like NOP will take 5T instead of regular 4T and DMA transfer configured to 2T+2T will take 3T+2T instead), there is some chance this may be improved in the future.