Difference between revisions of "Anti-brick Register"
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|ShortDesc=Used within the [[Anti-brick system]]. | |ShortDesc=Used within the [[Anti-brick system]]. | ||
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'''Read''' bit mapped: | '''Read''' bit mapped: | ||
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Revision as of 23:16, 19 April 2019
| Number | $10 |
|---|---|
| Readable | Yes |
| Writable | Yes |
| Short Description | Used within the Anti-brick system. |
Read bit mapped:
| Bit | Effect |
|---|---|
| 7-2 | Reserved, 0 |
| 1 | DivMMC button pressed |
| 0 | Multiface button pressed |
Write bit mapped (only in config mode):
| Bit | Effect |
|---|---|
| 7 | If 1 start selected core, if 0 FPGA loads the fixed anti-brick core |
| 6-5 | Reserved, must be 0 |
| 4-0 | Core ID 0-31 (default is 2) |
Note that in normal running pressing the DivMMC or Multiface button creates an NMI which halts any running program, and the reflashable core must be loaded before any user code is run. This means that unless you are rewriting the entire firmware from scratch this register is probably not useful.