Difference between revisions of "Layer 2 Access Port"
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{{Port | {{Port | ||
|Number=$123B | |Number=$123B | ||
| − | | | + | |NumberDec=4667 |
|PortMask=%0001 0010 0011 1011 ?? | |PortMask=%0001 0010 0011 1011 ?? | ||
| − | |Readable= | + | |ShortDesc=Enables [[Layer 2]] and controls paging of layer 2 screen into lower memory. |
| − | |Writable= | + | |Readable=Yes |
| + | |Writable=Yes | ||
|Subsystem=Layer 2 | |Subsystem=Layer 2 | ||
}} | }} | ||
| + | Read or write-with-bit-4-zero (soft reset = 0): | ||
| + | |||
| + | {| class="wikitable" | ||
| + | ! Bit !! Description | ||
| + | |- | ||
| + | | 7-6 || Video RAM bank select (write/read paging) | ||
| + | 00 = first 16K of layer 2 in the bottom 16K | ||
| + | 01 = second 16K of layer 2 in the bottom 16K | ||
| + | 10 = third 16K of layer 2 in the bottom 16K | ||
| + | 11 = first 48K of layer 2 in the bottom 48K (since core 3.0) | ||
| + | |- | ||
| + | | 5 || Reserved, write 0 | ||
| + | |- | ||
| + | | 4 || 0 | ||
| + | |- | ||
| + | | 3 || 0 = map {{NextRegNo|$12}}, 1 = map {{NextRegNo|$13}} | ||
| + | |- | ||
| + | | 2 || Enable mapping for memory reads | ||
| + | |- | ||
| + | | 1 || Layer 2 visible - {{NextRegNo|$12}} | ||
| + | Since core 3.0 this bit has mirror in {{NextRegNo|$69}} | ||
| + | |- | ||
| + | | 0 || Enable mapping for memory writes | ||
| + | |} | ||
| + | |||
| + | The Layer 2 data being displayed are always driven by {{NextRegNo|$12}}, the "shadow" register $13 does affect only the memory mapping feature (when bit 3 is set), never the display data (to "flip" the data being displayed, write new bank value into register $12). | ||
| + | |||
| + | Write-with-bit-4-set (since core 3.0.7) (soft reset = 0): | ||
| + | |||
| + | {| class="wikitable" | ||
| + | ! Bit !! Description | ||
| + | |- | ||
| + | | 7-5 || Reserved, write 0 | ||
| + | |- | ||
| + | | 4 || 1 | ||
| + | |- | ||
| + | | 3 || Reserved, write 0 | ||
| + | |- | ||
| + | | 2-0 || 16ki bank relative offset (+0 .. +7) applied to Layer 2 memory mapping | ||
| + | |} | ||
| + | |||
| + | The bit 4 = 1 functionality was added in core 3.0.7 together with new Layer 2 display modes, most likely usage is to set up mapping like %00'00'??'1'? or %11'00'??'1'? to map first bank into bottom 16ki or 48ki of memory, then switching the mapped bank by writing relative offset value 0..7 to the port with bit 4 set, like %0001'0011 to modify mapping to start with fourth (+3) bank of Layer 2. The original mapping mode did cover only first three banks (which covers whole 256x192 Layer 2 mode), but the new Layer 2 modes 320x256x8bpp and 640x256x4bpp occupy full five 16kiB banks, this new relative offsetting can be used to reach any of the five banks even when "first bank into bottom 16ki" type of mapping is selected. | ||
Latest revision as of 11:02, 4 May 2020
| Number | $123B |
|---|---|
| Decimal | 4667 |
| Short desc. | Enables Layer 2 and controls paging of layer 2 screen into lower memory. |
| Bit Mask | %0001 0010 0011 1011 ?? |
| Readable | Yes |
| Writable | Yes |
| Subsystem | Layer 2 |
Read or write-with-bit-4-zero (soft reset = 0):
| Bit | Description |
|---|---|
| 7-6 | Video RAM bank select (write/read paging)
00 = first 16K of layer 2 in the bottom 16K 01 = second 16K of layer 2 in the bottom 16K 10 = third 16K of layer 2 in the bottom 16K 11 = first 48K of layer 2 in the bottom 48K (since core 3.0) |
| 5 | Reserved, write 0 |
| 4 | 0 |
| 3 | 0 = map Layer 2 RAM Page Register ($12), 1 = map Layer 2 RAM Shadow Page Register ($13) |
| 2 | Enable mapping for memory reads |
| 1 | Layer 2 visible - Layer 2 RAM Page Register ($12)
Since core 3.0 this bit has mirror in Display Control 1 Register ($69) |
| 0 | Enable mapping for memory writes |
The Layer 2 data being displayed are always driven by Layer 2 RAM Page Register ($12), the "shadow" register $13 does affect only the memory mapping feature (when bit 3 is set), never the display data (to "flip" the data being displayed, write new bank value into register $12).
Write-with-bit-4-set (since core 3.0.7) (soft reset = 0):
| Bit | Description |
|---|---|
| 7-5 | Reserved, write 0 |
| 4 | 1 |
| 3 | Reserved, write 0 |
| 2-0 | 16ki bank relative offset (+0 .. +7) applied to Layer 2 memory mapping |
The bit 4 = 1 functionality was added in core 3.0.7 together with new Layer 2 display modes, most likely usage is to set up mapping like %00'00'??'1'? or %11'00'??'1'? to map first bank into bottom 16ki or 48ki of memory, then switching the mapped bank by writing relative offset value 0..7 to the port with bit 4 set, like %0001'0011 to modify mapping to start with fourth (+3) bank of Layer 2. The original mapping mode did cover only first three banks (which covers whole 256x192 Layer 2 mode), but the new Layer 2 modes 320x256x8bpp and 640x256x4bpp occupy full five 16kiB banks, this new relative offsetting can be used to reach any of the five banks even when "first bank into bottom 16ki" type of mapping is selected.